LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 113
LPC4350FET256,551
Manufacturer Part Number
LPC4350FET256,551
Description
IC MCU 32BIT 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4350FET256,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
146
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
264K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4350FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 17.
C
[1]
[2]
[3]
[4]
[5]
LPC4350_30_20_10
Objective data sheet
Symbol
t
t
t
BLSLBLSH
BLSHEOW
BLSHDNV
Fig 33. External static memory read/write access (PB = 0)
L
= 30 pF, T
Parameters are shown as RD
Parameters specified for 40 % of V
Latest of address valid, CS LOW, OE LOW, BLSx LOW (PB = 1).
After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid.
End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH (PB = 1).
EMC_BLSx
EMC_CSx
EMC_WE
EMC_OE
EMC_Ax
EMC_Dx
Dynamic characteristics: Static external memory interface
Parameter
BLS LOW to BLS HIGH time WR
BLS HIGH to end of write
time
BLS HIGH to data invalid
time
amb
=
40
[1]
C to 85
n
or WD
C, V
DD(IO)
RD
DD(REG)(3V3)
RD
n
2
in
1
for rising edges and 60 % of V
Figure 33
RD
Conditions
WR
WR12;
PB = 0
All information provided in this document is subject to legal disclaimers.
5
10
11
; PB = 0
Rev. 2.1 — 23 September 2011
; PB = 0
RD
= <tbd>.
RD
as indicated in the Conditions column.
5
RD
5
4
[1]
[5]
Min
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
EOR
RD
RD
DD(IO)
6
+ <tbd>
7
for falling edges.
WR
…continued
32-bit ARM Cortex-M4/M0 microcontroller
WR
2
9
Typ
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
LPC4350/30/20/10
WR
WR
1
10
+ <tbd>
WR
12
WR
11
Max
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
EOW
© NXP B.V. 2011. All rights reserved.
+ <tbd>
WR
002aag214
8
113 of 145
Unit
ns
ns
ns
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