LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 67

• Manufacturer Part Number: LPC4350FET256,551
• Description: IC MCU 32BIT 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4350FET256,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 146
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 264K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.6.2 Interrupt sources
7.8.1 Features
7.10 On-chip static RAM
7.7 Event router
7.8 Global Input Multiplexer Array (GIMA)
7.9 System Tick timer (SysTick)
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up
signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,
and Deep power-down modes. Individual events can be configured as edge or level
sensitive and can be enabled or disabled in the event router. The event router can be
battery powered.
The following events if enabled in the event router can create a wake-up signal and/or an
interrupt:
The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers,
event router, or the ADCs.
The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
The LPC4350/30/20/10 support up to 200 kB local SRAM and an additional 64 kB AHB
SRAM with separate bus master access for higher throughput and individual power
control for low power operation.
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Software interrupt generation.
External pins WAKEUP0/1/2/3 and RESET
Alarm timer, RTC, WWDT, BOD interrupts
C_CAN and QEI interrupts
Ethernet, USB0, USB1 signals
Selected outputs of combined timers (SCT and timer0/1/3)
Single selection of a source.
Signal inversion.
Can capture a pulse if the input event source is faster than the target clock.
Synchronization of input event and target clock.
Single-cycle pulse generation for target.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2011. All rights reserved.
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