CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 26

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O
determines the right port data I/O sequencing order (Big Endian
or Little Endian).
During word (18-bit) bus size operation, a logic LOW applied to
the BE pin will select Little Endian operation. In this case, the
least significant data word is read from the right port first or
written to the right port first. A logic “1” on the BE pin during word
(18-bit) bus size operation will select Big Endian operation
resulting in the most significant data word being transferred
through the right port first. Internally, the data will be stored in the
appropriate 36-bit LSB or MSB I/O memory location. Device
operation requires a minimum of two clock cycles to read or write
during word (18-bit) bus size operation. An internal sub-counter
automatically increments the right port multiplexer control when
Little or Big Endian operation is in effect.
Document Number: 38-06054 Rev. *E
0R–17R
. The level applied to the Big Endian (BE) pin
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, 9 bits of data are ported
through I/O
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin (BE)
under these circumstances will determine the right port data I/O
sequencing order (Big or Little Endian). A logic LOW applied to
the BE pin during byte (9-bit) bus size operation will select Little
Endian operation. In this case, the least significant data byte is
read from the right port first or written to the right port first. A logic
“1” on the BE pin during byte (9-bit) bus size operation will select
Big Endian operation resulting in the most significant data word
to be transferred through the right port first. Internally, the data
will be stored in the appropriate 36-bit LSB or MSB I/O memory
location. Device operation requires a minimum of four clock
cycles to read or write during byte (9-bit) bus size operation. An
internal sub-counter automatically increments the right port
multiplexer control when Little or Big Endian operation is in
effect. When transferring data in byte (9-bit) bus match format,
the unused I/O pins (I/O
0R–8R
.
9RQ–35R
) are three-stated.
CY7C09569V
CY7C09579V
Page 26 of 32
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