CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 14

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Pipelined Read-to-Write-to-Read (OE Controlled)
Notes
Document Number: 38-06054 Rev. *E
31. Test conditions used are Load 2.
32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
33. CE = ADS = CNTEN = V
34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Data
Address
Data
CLK
R/W
OUT
OE
CE
IN
t
t
t
SW
SC
SA
A
IL
n
; CNTRST = V
t
CH2
t
CYC2
t
t
t
HW
HC
HA
(continued)
t
CL2
IH
.
A
Read
n+1
t
CD2
Q
t
OHZ
n
t
SW
t
SD
D
A
n+2
[31, 32, 33, 34]
n+2
t
HW
t
HD
A
D
Write
n+3
n+3
A
n+4
t
CKLZ
Read
CY7C09569V
CY7C09579V
A
n+5
t
CD2
Page 14 of 32
Q
n+4
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