CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 11

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Bus Match Read Cycle for Flow-Through Output (FT/PIPE = V
Bus Match Read Cycle for Pipelined Operation (FT/PIPE = V
Notes
Document Number: 38-06054 Rev. *E
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. The output is disabled (high-impedance state) by CE=V
18. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
19. See table “Right Port Operation“ for data output on first and subsequent cycles.
20. CNTEN = V
Data
Data
Address
all the time except when loading the initial external address (i.e. ADS = V
Address
ADS
ADS
CLK
R/W
OUT
OE
OUT
R/W
CLK
OE
CE
CE
LOW
IL
. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V
LOW
t
t
t
t
SC
SC
SW
SA
t
t
SA
SW
A
A
n
n
t
t
HA
HW
t
CH2
t
t
t
t
t
HC
HW
HA
HC
CH1
t
CKLZ
t
CYC2
(continued)
t
CD1
t
CYC1
1 Latency
t
CL2
t
CL1
A
n
t
CLKZ
A
IH
n
following the next rising edge of the clock.
Cycle
t
DC
1st
Q
t
CD2
n
IL
only required when reading or writing the first Byte or Word).
1st Cycle
A
n+1
Q
n
t
A
DC
n+1
IH
IL
)
t
CD2
[16, 17, 18, 19, 20]
)
Cycle
[16, 17, 18, 19, 20]
Q
2nd
n
2nd Cycle
A
Q
n+1
n
t
DC
A
n+1
t
CD2
Cycle
Q
1st
t
DC
n+1
1st Cycle
CY7C09569V
CY7C09579V
Q
n+1
t
DC
Cycle
Q
Page 11 of 32
2nd
n+1
IH
level
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