CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 16

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Flow-Through Read-to-Write-to-Read (OE = V
Flow-Through Read-to-Write-to-Read (OE Controlled)
Notes
Document Number: 38-06054 Rev. *E
42. ADS = V
43. Addresses do not have to be accessed sequentially since ADS = V
44. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
45. See table “Right Port Operation“ for data output on first and subsequent cycles.
46. CE = ADS = CNTEN = V
47. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
48. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
Data
Address
Data
Address
Data
Data
CLK
R/W
OUT
CLK
R/W
OE
OUT
CE
CE
IN
IN
IL
, CNTEN = V
t
t
t
t
SW
SW
SA
SA
IL
IL
A
and CNTRST = V
A
; CNTRST = V
n
n
t
t
t
t
CD1
CD1
CH1
CH1
t
t
CYC1
CYC1
t
t
t
t
(continued)
HW
HW
HA
HA
t
t
CL1
CL1
IH
Q
.
IH
n
t
Q
DC
.
n
A
A
n+1
n+1
Read
Read
t
DC
t
CD1
t
t
SW
SD
t
OHZ
IL
t
CKHZ
IL
)
Q
[42, 43, 44, 45, 46, 47]
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
A
n+1
A
D
n+2
n+2
n+2
[42 , 43, 46, 47, 48]
Operation
t
No
t
HW
HD
t
t
SW
SD
Write
A
D
A
D
n+2
n+2
n+3
n+3
Write
t
t
HW
HD
A
A
n+4
n+3
t
OE
t
t
CKLZ
t
CKLZ
t
CD1
CD1
Read
Read
Q
t
Q
t
DC
DC
CY7C09569V
CY7C09579V
n+3
A
n+4
A
n+4
n+5
t
t
CD1
CD1
Page 16 of 32
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