CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 2

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Document Number: 38-06054 Rev. *E
Note
Logic Block Diagram
1. A
R/W
OE
B
CE
FT/Pipe
I/O
I/O
I/O
I/O
A
CLK
ADS
CNTEN
CNTRST
0
0
–B
–A
L
0L
9L
18L
27L
L
0
–A
L
L
L
–I/O
–I/O
3
13/14L
–I/O
–I/O
13
L
L
for 16K; A
8L
17L
L
26L
35L
[1]
0
–A
14/15
14
for 32 K devices.
Counter/
Register
Address
Decode
9
9
9
9
Control
Logic
Port
Left
Control
I/O
True Dual-Ported
RAM Array
Control
I/O
Control
9
9
9
9
Logic
Right
Port
Counter/
Address
Register
Decode
Match
Bus
14/15
9/18/36
CY7C09569V
CY7C09579V
A
CNTRST
FT/Pipe
0
CNTEN
–A
BE
SIZE
R/W
BM
Page 2 of 32
I/O
ADS
13/14R
CLK
OE
CE
R
R
R
R
R
R
R
R
R
[1]
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