CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 21

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Counter Reset (Flow-Through Outputs)
Notes
Document Number: 38-06054 Rev. *E
64. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
65. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
66. CE = B0 = B1 = B2 = B3 = V
67. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
CNTRST
Data
during a valid WRITE cycle.
Address
CNTEN
Address
Internal
Data
R/W
ADS
CLK
OUT
IN
A
t
SRST
X
t
HRST
t
CH2
IL
.
Counter
Reset
t
CYC2
(continued)
t
CL2
t
t
SD
SW
D
0
t
t
HD
HW
Address 0
[64, 65, 66, 67, 68]
Write
0
Address 0
t
CD1
Read
Q
0
Address 1
Read
t
SA
1
OUT
A
Q
n
1
should be in the High-Impedance state
t
HA
Address n
Read
A
A
n
n+1
CY7C09569V
CY7C09579V
Q
n
Page 21 of 32
A
n+1
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