CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 20

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Counter Reset (Pipelined Outputs)
Notes
Document Number: 38-06054 Rev. *E
59. Test conditions used are Load 2.
60. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
61. CE = B0 = B1 = B2 = B3 = V
62. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
63. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
CNTRST
Data
during a valid WRITE cycle.
Address
Address
CNTEN
Internal
Data
ADS
R/W
CLK
OUT
[63]
IN
t
SRST
A
x
t
HRST
t
CH2
Counter
Reset
t
CYC2
IL
.
t
CL2
t
SW
t
SD
(continued)
D
0
t
t
HW
HD
Address 0
Write
[59, 60, 61, 62, 63]
0
t
CKLZ
Address 0
Read
t
CD2
Address 1
Read
1
Q
A
0
n
Address A
t
CD2
Read
OUT
should be in the High-Impedance state
A
n
t
SA
n
A
Q
m
1
t
HA
Address A
Read
CY7C09569V
CY7C09579V
A
m
m
Q
A
n
p
Page 20 of 32
A
p
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