CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 23

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Read/Write and Enable Operation
Address Counter Control Operation
Document Number: 38-06054 Rev. *E
Notes
Address
73. “X” = “Don’t Care,” “H” = V
74. ADS, CNTEN, CNTRST = “Don’t Care.”
75. OE is an asynchronous input signal.
76. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
77. Counter operation is independent of CE.
A
A
OE
X
X
X
X
X
H
L
n
n
Previous
Address
A
A
A
X
X
n
n
n
CLK
X
IH
CLK
Inputs
, “L” = V
IL
.
OE
CE
X
X
X
X
L
H
L
L
L
R/W
X
X
H
X
X
[73, 74, 75]
R/W
H
X
L
X
[73, 77]
ADS
H
H
X
L
L
CNTEN
H
H
X
L
L
I/O
Outputs
High Z
High Z
D
0
D
OUT
–I/O
CNTRST
IN
35
H
H
H
H
L
Increment Counter increment
Hold +
Mode
Reset
Read
Load
Hold
Deselected
Write
Read
Outputs disabled
[76]
Counter reset
Address load into counter
External address blocked -
counter address readout
External address blocked -
counter disabled
[76]
Operation
Operation
CY7C09569V
CY7C09579V
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