CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 22

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Pipelined Read of State of Address Counter
Flow-Through Read of State of Address Counter
Notes
Document Number: 38-06054 Rev. *E
Internal
Address
69. CE = OE = V
70. When reading ADDRESS
71. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3
72. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.
Data
Internal
Address
Data
CNTEN
Address
Address
consecutive cycles for x9 mode.
CNTEN
ADS
OUT
OUT
CLK
ADS
CLK
t
t
SCN
IL
SAD
t
t
SCN
SAD
; R/W = CNTRST = V
t
t
SA
SA
Q
A
A
x-2
Q
t
n
t
n
t
HAD
HCN
t
x
t
t
HA
HA
HCN
HAD
t
t
CH2
External
CH1
Address
Load
External
Address
t
OUT
CYC2
Load
t
CYC1
t
SCN
in x9 Bus Match mode, readout of A
t
t
CL2
t
CL1
SCN
IH
(continued)
Q
.
Q
x-1
t
HCN
Read Counter Address
A
n
Read Counter Address
t
n
DC
t
t
CA1
HCN
A
n
Q
A
n
n
t
DC
[69, 70, 71]
t
CA2
N
is extended by 1 cycle.
[69, 70, 72]
A
n+1
A
Q
n
n+1
Read with
Counter
Read with
Counter
t
t
SAD
t
SCN
SAD
t
t
HCN
HAD
t
A
A
HAD
n+2
n+1
Counter
Q
Counter
Hold
Hold
n+2
t
SCN
t
HCN
Q
n+1
Read With Counter
Read with Counter
CY7C09569V
CY7C09579V
A
A
n+3
n+2
Q
n+3
Page 22 of 32
Q
n+2
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