CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 18

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CY7C09579V-100AC

Manufacturer Part Number
CY7C09579V-100AC
Description
SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C09579V-100AC

Package
144TQFP
Timing Type
Synchronous
Density
1.125 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
3.3 V
Address Bus Width
15 Bit
Number Of I/o Lines
36 Bit
Number Of Ports
2
Number Of Words
32K
Switching Waveforms
Pipelined Read with Address Counter Advance
Flow-Through Read with Address Counter Advance
Note
Document Number: 38-06054 Rev. *E
56. CE = OE = V
Data
Data
Address
Address
CNTEN
CNTEN
ADS
ADS
CLK
CLK
OUT
OUT
t
t
t
SAD
SCN
SA
t
t
SAD
SCN
t
SA
IL
; R/W = CNTRST = V
Q
A
x–1
n
A
Q
t
n
CH2
x
t
DC
External
Address
t
CH1
Read
External
Address
Read
t
CYC2
t
t
t
CD1
t
HAD
HCN
t
HA
CYC1
t
t
HCN
t
HAD
HA
t
IH
(continued)
CL2
.
t
CL1
Q
Q
x
t
DC
n
t
CD2
Read with Counter
Read with Counter
Q
[56]
n
Q
n+1
[56]
t
t
SCN
SAD
Q
n+1
Counter Hold
Counter Hold
t
t
HCN
t
HAD
t
SAD
SCN
Q
n+2
t
DC
Q
t
n+2
CD1
t
t
HAD
HCN
Read with Counter
Counter
Read
with
Q
CY7C09569V
CY7C09579V
n+3
t
DC
t
CD1
Page 18 of 32
Q
Q
n+3
n+4
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