CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 17

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Bus Match Flow-Through Read-to-Write-to-Read (OE = V
Notes
Document Number: 38-06054 Rev. *E
49. Test conditions used are Load 2.
50. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
51. See table “Right Port Operation“ for data output on first and subsequent cycles.
52. CNTEN = V
53. CE = ADS = CNTEN = V
54. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
55. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
all the time except when loading the initial external address (i.e. ADS = V
Address
Data
Data
CLK
ADS
R/W
CE
OUT
IN
IL
. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V
t
t
t
SC
SW
SA
A
n
t
t
t
t
HC
HW
HA
CH1
IL
1st Cycle
t
; CNTRST = V
CD1
t
CYC1
Read
t
CL1
1st Word
(continued)
A
Q
n
n
t
IH
DC
2nd Cycle
.
t
CD1
Read
2nd Word
A
Q
n+1
t
n
CKHZ
Operation
No
t
SW
t
1st Word
SD
A
D
n+1
IL
n+1
t
only required when reading or writing the first Byte or Word).
HW
t
HD
1st Cycle
Write
IL
2nd Word
)
[49, 50, 51, 52, 53, 54, 55]
A
D
n+1
n+1
2nd Cycle
Write
A
n+1
t
1st Cycle
CD1
t
CKLZ
Read
A
Q
n+1
n+1
2nd Cycle
t
CD1
Read
t
DC
CY7C09569V
CY7C09579V
A
Q
n+2
n+1
Page 17 of 32
IH
level
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