ISP1562BE STEricsson, ISP1562BE Datasheet - Page 63

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 94.
Address: Content of the base address register + 20h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 24
23 to 16
15 to 8
7
6
The reserved bits should always be written with the reset value.
USBCMD - USB Command register bit description
Symbol
reserved
ITC[7:0]
reserved
LHCR
IAAD
LHCR
R/W
R/W
15
0
7
0
Description
-
Interrupt Threshold Control: Default = 08h. This field is used by the system software to select
the maximum rate at which the host controller will issue interrupts. If software writes an invalid
value to this register, the results are undefined. Valid values are:
00h — reserved
01h — 1 microframe
02h — 2 microframes
04h — 4 microframes
08h — 8 microframes (equals 1 ms)
10h — 16 microframes (equals 2 ms)
20h — 32 microframes (equals 4 ms)
40h — 64 microframes (equals 8 ms)
Software modifications to this field while HCH (bit 12) in the USBSTS register is zero results in
undefined behavior.
-
Light Host Controller Reset: This control bit is not required. It allows the driver software to reset
the EHCI controller, without affecting the state of the ports or the relationship to the companion
host controllers. If not implemented, a read of this field will always return zero. If implemented, on
read:
0 — Indicates that the Light Host Controller Reset has completed and it is ready for the host
software to re-initialize the host controller.
1 — Indicates that the Light Host Controller Reset has not yet completed.
Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to
notify the host controller to issue an interrupt the next time it advances the asynchronous
schedule. Software must write logic 1 to this bit to ring the doorbell. When the host controller has
evicted all appropriate cached schedule states, it sets IAA (bit 5 in the USBSTS register). If IAAE
(bit 5 in the USBINTR register) is logic 1, then the host controller will assert an interrupt at the next
interrupt threshold. The host controller sets this bit to logic 0 after it sets IAA. Software must not
set this bit when the asynchronous schedule is inactive because this results in an undefined value.
IAAD
R/W
R/W
14
0
6
0
R/W
ASE
R/W
13
0
5
0
Rev. 03 — 14 November 2008
PSE
R/W
R/W
12
0
4
0
reserved
[1]
R/W
R/W
11
0
3
0
FLS[1:0]
R/W
R/W
10
0
2
0
HS USB PCI host controller
RESET
R/W
R/W
HC
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
RS
8
0
0
0
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