ISP1562BE STEricsson, ISP1562BE Datasheet - Page 52

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 78.
Address: Content of the base address register + 44h
Table 79.
Address: Content of the base address register + 48h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 12
11 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
reserved
LST[11:0]
HcLSThreshold - Host Controller Low-Speed Threshold register bit description
HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation
11.1.19 HcRhDescriptorA register
R/W
R/W
R/W
R/W
R/W
R/W
23
15
31
23
15
0
0
7
0
1
0
0
Description
-
Low-Speed Threshold: This field contains a value that is compared to the FR[13:0] field, before
initiating a low-speed transaction. The transaction is started only if FR
calculated by the HCD, considering the transmission and set-up overhead.
This register is the first of two registers describing the characteristics of the root hub.
Reset values are implementation-specific.
Table 79
reserved
R/W
R/W
R/W
R/W
R/W
R/W
22
14
30
22
14
0
0
6
0
1
0
0
contains the bit allocation of the HcRhDescriptorA register.
reserved
[1]
[1]
R/W
R/W
R/W
R/W
R/W
R/W
21
13
29
21
13
0
0
5
1
1
0
0
Rev. 03 — 14 November 2008
NOCP
R/W
R/W
R/W
R/W
R/W
R/W
20
12
28
20
12
0
0
4
0
1
0
0
POTPGT[7:0]
reserved
reserved
LST[7:0]
[1]
[1]
OCPM
R/W
R/W
R/W
R/W
R/W
R/W
19
11
27
19
11
0
0
3
1
1
0
1
R/W
R/W
R/W
R/W
R/W
DT
18
10
26
18
10
R
0
1
2
0
1
0
0
LST[11:8]
HS USB PCI host controller
this field. The value is
NPS
R/W
R/W
R/W
R/W
R/W
R/W
17
25
17
0
9
1
1
0
1
0
9
0
© NXP B.V. 2008. All rights reserved.
ISP1562
PSM
R/W
R/W
R/W
R/W
R/W
R/W
16
24
16
0
8
0
0
0
1
0
8
1
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