ISP1562BE STEricsson, ISP1562BE Datasheet - Page 44

no-image

ISP1562BE

Manufacturer Part Number
ISP1562BE
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1562BE

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1562BE
Manufacturer:
PHILIPS
Quantity:
11 200
Part Number:
ISP1562BE
Manufacturer:
NXP
Quantity:
4 000
Part Number:
ISP1562BE
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Company:
Part Number:
ISP1562BE
Quantity:
7
Part Number:
ISP1562BEGA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1562BEGE
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1562BEUM
Manufacturer:
IDT
Quantity:
388
Part Number:
ISP1562BEUM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 57.
Address: Content of the base address register + 1Ch
Table 58.
Address: Content of the base address register + 1Ch
Table 59.
Address: Content of the base address register + 20h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
PCED[27:0]
reserved
HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation
HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation
11.1.9 HcControlHeadED register
31
23
15
31
23
15
R
R
R
R
R
R
R
0
0
0
7
0
0
0
0
The HcControlHeadED register contains the physical address of the first ED of the control
list. The bit allocation is given in
Description
Period Current ED: This is used by the host controller to point to the head of one of the periodic
lists that must be processed in the current frame. The content of this register is updated by the
host controller after a periodic ED is processed. The HCD may read the content in determining
which ED is being processed at the time of reading.
-
30
22
14
30
22
14
R
R
R
R
R
R
R
0
0
0
6
0
0
0
0
PCED[3:0]
29
21
13
29
21
13
R
R
R
R
R
R
R
0
0
0
5
0
0
0
0
Rev. 03 — 14 November 2008
28
20
12
28
20
12
R
R
R
R
Table
R
R
R
0
0
0
4
0
0
0
0
CHED[27:20]
CHED[19:12]
PCED[27:20]
PCED[19:12]
PCED[11:4]
CHED[11:4]
59.
27
19
11
27
19
11
R
R
R
R
R
R
R
0
0
0
3
0
0
0
0
26
18
10
26
18
10
R
R
R
R
R
R
R
0
0
0
2
0
0
0
0
HS USB PCI host controller
reserved
25
17
25
17
R
R
R
R
R
R
R
0
0
9
0
1
0
0
0
9
0
© NXP B.V. 2008. All rights reserved.
ISP1562
24
16
24
16
R
R
R
R
R
R
R
0
0
8
0
0
0
0
0
8
0
43 of 93

Related parts for ISP1562BE