ISP1562BE STEricsson, ISP1562BE Datasheet - Page 38

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 48.
Address: Content of the base address register + 08h
Table 49.
Address: Content of the base address register + 0Ch
ISP1562_3
Product data sheet
Bit
31 to 18
17 to 16
15 to 4
3
2
1
0
Bit
Symbol
Reset
Access
HcCommandStatus - Host Controller Command Status register bit description
Symbol
reserved -
SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is initialized
reserved -
OCR
BLF
CLF
HCR
HcInterruptStatus - Host Controller Interrupt Status register bit allocation
11.1.4 HcInterruptStatus register
reserved
R/W
31
0
Description
to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is detected, even
if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor any persistent
scheduling problems.
Ownership Change Request: This bit is set by an OS HCD to request a change of control of the
host controller. When set, the host controller must set OC (bit 30 in HcInterruptStatus). After the
changeover, this bit is cleared and remains so until the next request from the OS HCD.
Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the
bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the host controller
begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the host
controller does not need to process the bulk list. If BLF is logic 1, the host controller must start
processing the bulk list and set BF to logic 0. If the host controller finds a TD on the list, then the host
controller must set BLF to logic 1, causing the bulk list processing to continue. If no TD is found on
the bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the host controller
completes processing the bulk list and the bulk list processing stops.
Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set
by the HCD whenever it adds a TD to an ED in the control list.
When the host controller begins to process the head of the control list, it checks CLF. If CLF is logic 0,
the host controller does not need to process the control list. If Control-Filled (CF) is logic 1, the host
controller needs to start processing the control list and set CLF to logic 0. If the host controller finds a
TD on the list, then the host controller must set CLF to logic 1, causing the control list processing to
continue. If no TD is found on the control list, and if the HCD does not set CLF, then CLF is still logic 0
when the host controller completes processing the control list and the control list processing stops.
Host Controller Reset: This bit is set by the HCD to initiate a software reset of the host controller.
Regardless of the functional state of the host controller, it moves to the USBSUSPEND state in which
most of the operational registers are reset, except those stated otherwise; for example, IR (bit 8) in
the HcControl register, and no host bus accesses are allowed. This bit is cleared by the host
controller on completing the reset operation. The reset operation must be completed within 10 s.
This bit, when set, must not cause a reset to the root hub and no subsequent reset signaling must be
asserted to its downstream ports.
[1]
This is a 4-byte register that provides the status of the events that cause hardware
interrupts. The bit allocation of the register is given in
host controller sets the corresponding bit in this register. When a bit becomes set, a
hardware interrupt is generated, if the interrupt is enabled in the HcInterruptEnable
register (see
clear specific bits in this register by writing logic 1 to the bit positions to be cleared. The
HCD may not set any of these bits. The host controller does not clear the bit.
R/W
OC
30
0
Table
R/W
51) and the MIE (Master Interrupt Enable) bit is set. The HCD may
29
0
Rev. 03 — 14 November 2008
R/W
28
0
R/W
27
0
reserved
Table
[1]
R/W
26
0
49. When an event occurs, the
HS USB PCI host controller
R/W
25
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
24
0
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