ISP1562BE STEricsson, ISP1562BE Datasheet - Page 39

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 50.
Address: Content of the base address register + 0Ch
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30
29 to 7
6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
Symbol
reserved
OC
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptStatus - Host Controller Interrupt Status register bit description
11.1.5 HcInterruptEnable register
reserved
R/W
R/W
R/W
23
15
0
0
7
0
Description
-
Ownership Change: This bit is set by the host controller when HCD sets OCR (bit 3) in the
HcCommandStatus register. This event, when unmasked, will always immediately generate a System
Management Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not implemented.
-
Root Hub Status Change: This bit is set when the content of HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
Frame Number Overflow: This bit is set when the Most Significant Bit (MSB) of HcFmNumber
(bit 15) changes value, or after the HccaFrameNumber is updated.
Unrecoverable Error: This bit is set when the host controller detects a system error not related to
USB. The host controller must not proceed with any processing nor signaling before the system error
is corrected. The HCD clears this bit after the host controller is reset.
Resume Detected: This bit is set when the host controller detects that a device on the USB is
asserting resume signaling. This bit is set by the transition from no resume signaling to resume
signaling. This bit is not set when the HCD sets the USBRESUME state.
Start-of-Frame: At the start of each frame, this bit is set by the host controller and an SOF token is
generated at the same time.
Write-back Done Head: This bit is immediately set after the host controller has written HcDoneHead
to HccaDoneHead. Further, updates of HccaDoneHead occur only after this bit is cleared. The HCD
must only clear this bit after it has saved the content of HccaDoneHead.
Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the
update of HccaFrameNumber. A scheduling overrun increments the SOC[1:0] field (bits 17 to 16 of
HcCommandStatus).
[1]
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. A hardware interrupt is requested on the host
bus if the following conditions occur:
RHSC
R/W
R/W
R/W
22
14
0
0
6
0
FNO
R/W
R/W
R/W
21
13
0
0
5
0
Rev. 03 — 14 November 2008
R/W
R/W
R/W
UE
20
12
0
0
4
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
RD
19
11
0
0
3
0
R/W
R/W
R/W
SF
18
10
0
0
2
0
HS USB PCI host controller
WDH
R/W
R/W
R/W
17
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
R/W
SO
16
0
8
0
0
0
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