ISP1562BE STEricsson, ISP1562BE Datasheet - Page 17

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 7.
ISP1562_3
Product data sheet
Bit
15 to 10
9
8
7
6
5
4
3
2
1
0
CMD - Command register (address 04h) bit description
Symbol
reserved
FBBE
SERRE
SCTRL
PER
VGAPS
MWIE
SC
BM
MS
IOS
Description
-
Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back
transactions to various devices. The initialization software must set this bit if all targets are fast
back-to-back capable.
0 — Fast back-to-back transactions are only allowed to the same agent (value after RST#).
1 — The master is allowed to generate fast back-to-back transactions to different agents.
SERR# Enable: This bit is an enable bit for the SERR# driver. All devices that have an SERR#
pin must implement this bit. Address parity errors are reported only if this bit and the PER bit are
logic 1.
0 — Disable the SERR# driver.
1 — Enable the SERR# driver.
Stepping Control: This bit controls whether a device does address and data stepping. Devices
that never do stepping must clear this bit. Devices that always do stepping must set this bit.
Devices that can do either, must make this bit read and write, and initialize it to logic 1 after
RST#.
Parity Error Response: This bit controls the response of a device to parity errors. When the bit
is set, the device must take its normal action when a parity error is detected. When the bit is
logic 0, the device sets DPE (bit 15 in the Status register) when an error is detected, but does not
assert PERR# and continues normal operation. The state of this bit after RST# is logic 0.
Devices that check parity must implement this bit. Devices are required to generate parity, even if
parity checking is disabled.
VGA Palette Snoop: This bit controls how VGA compatible and graphics devices handle
accesses to VGA palette registers.
0 — The device must treat palette write accesses like all other accesses.
1 — Palette snooping is enabled, that is, the device does not respond to palette register writes
and snoops data.
VGA compatible devices must implement this bit.
Memory Write and Invalidate Enable: This is an enable bit for using the Memory Write and
Invalidate command.
0 — Memory writes must be used instead. State after RST# is logic 0.
1 — Masters may generate the command.
This bit must be implemented by master devices that can generate the Memory Write and
Invalidate command.
Special Cycles: Controls the action of a device on special cycle operations.
0 — Causes the device to ignore all special cycle operations. State after RST# is logic 0.
1 — Allows the device to monitor special cycle operations.
Bus Master: Controls the ability of a device to act as a master on the PCI bus.
0 — Disables the device from generating PCI accesses. State after RST# is logic 0.
1 — Allows the device to behave as a bus master.
Memory Space: Controls the response of a device to memory space accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to memory space accesses.
IO Space: Controls the response of a device to I/O space accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to I/O space accesses.
Rev. 03 — 14 November 2008
HS USB PCI host controller
© NXP B.V. 2008. All rights reserved.
ISP1562
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