ISP1562BE STEricsson, ISP1562BE Datasheet - Page 51

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 75.
Address: Content of the base address register + 40h
[1]
Table 76.
Address: Content of the base address register + 40h
Table 77.
Address: Content of the base address register + 44h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 14
13 to 0
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
reserved
P_S[13:0]
HcPeriodicStart - Host Controller Periodic Start register bit allocation
HcPeriodicStart - Host Controller Periodic Start register bit description
HcLSThreshold - Host Controller Low-Speed Threshold register bit allocation
11.1.17 HcPeriodicStart register
11.1.18 HcLSThreshold register
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
reserved
Description
-
Periodic Start: After a hardware reset, this field is cleared. It is then set by the HCD during the host
controller initialization. The value is roughly calculated as 10 % of HcFmInterval. A typical value is
3E67h. When HcFmRemaining reaches the value specified, processing of the periodic lists have
priority over control or bulk processing. The host controller, therefore, starts processing the interrupt
list after completing the current control or bulk transaction that is in progress.
This register has a 14-bit programmable value that determines when is the earliest time
for the host controller to start processing the periodic list. For bit allocation, see
This register contains an 11-bit value used by the host controller to determine whether to
commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the
host controller nor the HCD can change this value. For bit allocation, see
[1]
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 03 — 14 November 2008
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
reserved
reserved
reserved
P_S[7:0]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
R/W
27
19
11
27
0
0
0
3
0
0
P_S[13:8]
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
HS USB PCI host controller
R/W
R/W
R/W
R/W
R/W
25
17
25
0
0
9
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1562
Table
77.
Table
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0
50 of 93
75.