ISP1562BE STEricsson, ISP1562BE Datasheet - Page 48

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 68.
Address: Content of the base address register + 30h
Table 69.
Address: Content of the base address register + 34h
[1]
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 4 DH[27:0] Done Head: When a TD is completed, the host controller writes the content of HcDoneHead to the
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
Symbol
reserved -
HcDoneHead - Host Controller Done Head register bit description
HcFmInterval - Host Controller Frame Interval register bit allocation
11.1.14 HcFmInterval register
R/W
R/W
R/W
R/W
R/W
FIT
31
23
15
7
0
0
0
0
7
1
Description
NextTD field of the TD. The host controller then overwrites the content of HcDoneHead with the address
of this TD. This is set to logic 0 whenever the host controller writes the content of this register to HCCA.
reserved
This register contains a 14-bit value that indicates the bit time interval in a frame, that is,
between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum
packet size that the host controller may transmit or receive, without causing a scheduling
overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new
value over the present at each SOF. This provides the possibility for the host controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset. The bit allocation of the register is given in
[1]
R/W
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
6
1
DH[3:0]
R/W
R/W
R/W
R/W
R/W
29
21
13
5
0
0
0
1
5
0
Rev. 03 — 14 November 2008
R/W
R/W
R/W
R/W
R/W
28
20
12
4
0
0
0
0
4
1
FSMPS[7:0]
FI[7:0]
FSMPS[14:8]
R/W
R/W
R/W
R/W
R/W
27
19
11
3
0
0
0
1
3
1
FI[13:8]
Table
69.
R/W
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
1
2
1
reserved
HS USB PCI host controller
[1]
R/W
R/W
R/W
R/W
R/W
25
17
1
0
0
0
9
1
1
1
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
R/W
24
16
0
0
0
0
8
0
0
1
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