TE28F800B3B110 Intel, TE28F800B3B110 Datasheet - Page 57

• Manufacturer Part Number: TE28F800B3B110
• Manufacturer: Intel

Specifications of TE28F800B3B110

• Lead Free Status / Rohs Status: Not Compliant

11.3.1
Note:
11.4
Datasheet
Clearing the Status Register
The WSM sets status bits 1 through 7 to 1, and clears bits 2, 6, and 7 to 0. However, the WSM
cannot clear status bits 1 or 3 through 5 to 0.
Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through
the Clear Status Register (50H) command. By allowing the system software to control the resetting
of these bits, several operations can be performed (such as cumulatively programming several
addresses or erasing multiple blocks in sequence) before reading the Status Register to determine if
an error occurred during that series.
Clear the Status Register before beginning another command or sequence.
The Read Array command must be issued before data can be read from the flash memory array.
Program Mode
Programming is executed using a two-write sequence.
The WSM executes a sequence of internally timed events to program preferred bits of the
addressed location.
The WSM then verifies that the bits are sufficiently programmed.
Programming the memory changes specific bits within an address location to 0. If users attempt to
program 1 instead of 0, the memory cell contents do not change and no error occurs.
The Status Register indicates the programming status: while the program sequence executes, status
bit 7 is 0.
To poll the Status Register, toggle either CE# or OE#.
While programming, the only valid commands are:
When programming is complete, the program-status bits must be checked.
Clear the Status Register before attempting the next operation. Any CUI instruction can follow
after programming is completed; however, to prevent inadvertent Status Register reads, be sure to
reset the CUI to read-array mode.
1. The Program Setup command (40H) is written to the CUI.
2. A second write specifies the address and data to program.
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Read Status Register
Program Suspend
Program Resume
If the programming operation was unsuccessful, SR.4 is set, indicating a program failure.
If SR.3 is set, then V
program command.
If SR.1 is set, a program operation was attempted on a locked block and the operation aborted.
Intel
®
Order Number: 290580, Revision: 020
Advanced Boot Block Flash Memory (B3)
PP
was not within acceptable limits, and the WSM did not execute the
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
18 Aug 2005
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