TE28F800B3B110 Intel, TE28F800B3B110 Datasheet - Page 52

• Manufacturer Part Number: TE28F800B3B110
• Manufacturer: Intel

Specifications of TE28F800B3B110

• Lead Free Status / Rohs Status: Not Compliant

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
10.1.2
10.1.3
10.1.4
18 Aug 2005
52
Output Disable
When OE# is at a logic-high level (V
are placed in a high-impedance state.
Standby
Deselecting the flash memory device by bringing CE# to a logic-high level (V
in standby mode. Standby mode substantially reduces device power consumption, without any
latency for subsequent read accesses. In standby mode, outputs are placed in a high-impedance
state independent of OE#. If deselected during Program or Erase operation, the flash memory
device continues to consume active power until the Program or Erase operation is complete.
Deep Power-Down / Reset
From read mode, RP# at V
After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, and
the Status Register is set to 80H.
page 48 (A)
If RP# is taken low for time t
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data might be partially erased or written.
The abort process uses the following sequence:
As with any automated device, RP# must be asserted during system reset. When the system
finishes reset, the processor expects to read from the flash memory. Automated flash memories
provide status information when read during program or Block-Erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization cannot occur, because the flash
memory might be providing status information instead of array data.
Intel
this application, RP# is controlled by the same RESET# signal that resets the system CPU.
1. When RP# goes low, the flash memory device shuts down the operation in progress, a process
2. After this time t
3. In both cases, after returning from an aborted operation, the relevant time t
•
•
•
•
•
Deselects the flash memory.
Places output drivers in a high-impedance state.
Turns off all internal circuits.
After a return from reset, a time t
After a return from reset, a delay (t
that takes time t
gone high during t
page 48
Power-Down/Reset Operations Waveforms” on page 48
t
paragraph. However, in this case, these delays are referenced to the end of t
when RP# goes high.
®
PHEL
Flash memories allow proper CPU initialization after a system reset, using the RP# input. In
must elapse before initiating a Read or Write operation, as discussed in the previous
illustrates this case.
(B)), or enters reset mode (if RP# is still logic low after t
Intel
®
Order Number: 290580, Revision: 020
PLRH
PLRH
Advanced Boot Block Flash Memory (B3)
PLRH
, the flash memory device either resets to read-array mode (if RP# has
to complete.
IL
, see
PLPH
for time t
Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
during a Program or Erase operation, the operation aborts. The
IH
PHQV
), the flash memory device outputs are disabled. Output pins
PLPH
PHWL
is required until the initial read-access outputs are valid.
does the following:
or t
PHEL
) is required before a write can be initiated.
(C)).
PLRH
, see
IH
PHQV
) places the device
Figure 14 “Deep
PLRH
or t
rather than
Datasheet
PHWL
/