UJA1023T/2R04,512 NXP Semiconductors, UJA1023T/2R04,512 Datasheet - Page 25

• Manufacturer Part Number: UJA1023T/2R04,512
• Description: IC CAN/LIN I/O SLAVE 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1023T/2R04,512

• Applications: LIN Controller
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 6.5 V ~ 27 V
• Package / Case: 16-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281302512; UJA1023T/2R04; UJA1023T/2R04

NXP Semiconductors
UJA1023
Product data sheet
7.2.2.1 Configuration mode
7.2.2.2 Normal mode
7.2.2.3 Sleep mode
7.2.2.4 Limp home sleep mode
The Configuration mode can be seen as initial state after power-on or undervoltage
detection. The UJA1023 configuration values are in the default settings. The I/O
pins P0 to P7 (Px) are set to high-impedance behavior and the INH is in its External
regulator mode, which outputs a HIGH-level in order to switch on an external voltage
regulator.
In Configuration mode the UJA1023 is not configured and it has no valid identifier and,
depending on the configuration pins, a default NAD. Thus, with the exception of the
MasterReq command, all LIN slave commands are disabled. Once the UJA1023 NAD is
assigned, via the assign NAD request, or the default NAD is used for the first time, the
Normal mode is entered. If a LIN bus failure is present (bus idle time-out or bus dominant
time-out) or the sleep command has been received, the UJA1023 enters its low-power
(Limp home) mode.
In Normal mode the UJA1023 receives and/or transmits input/output data as well as
configuration data.
A UJA1023 in Configuration mode enters the Normal mode only after its NAD assignment
or the first usage of the default NAD. After a NAD reconfiguration, all ports that are
configured in Output mode will be set to high-impedance.
Coming from Sleep mode or Limp home sleep mode the Normal mode can be entered via
local or remote wake-up. The output register of each I/O pin P0 to P7 (PxOut) keeps its
values of the Sleep mode or Limp home sleep mode. If the INH is in External regulator
mode, it outputs a HIGH-level to switch on an external voltage regulator.
For a mode transition from Standby mode to Normal mode the diagnostic data must be
read via a SlaveResp. With this request the master acknowledges the previous failure.
The PxOut registers keep their limp home values.
The UJA1023 enters its Sleep mode when the ‘Sleep mode command’ has been received
and the limp home sleep bit LSLP is reset (LSLP = 0). In Sleep mode the UJA1023 keeps
the current status on its Px. The INH will switch to high-impedance state.
After a local wake-up event the UJA1023 sends a ‘wake-up signal’ to wake up the master.
In Sleep mode the PWM and ADC are reset. The first LIN message will be lost due to
waking up the UJA1023.
Some applications may need dedicated HIGH and/or LOW output levels during Sleep
mode in order to achieve the lowest power dissipation of the application. Therefore the
UJA1023 provides the Limp home sleep mode (LH sleep mode). By enabling the LSLP
bit, the LH sleep mode output behavior can be configured. The LH sleep mode is enabled
if the configuration bit LSLP (D3.5) is set (LSLP = 1, see
After a local wake-up event the UJA1023 sends a ‘wake-up signal’ to wake up the master.
In the LH sleep mode the output registers (PxOut) of the UJA1023 are loaded with the
limp home value. After a wake-up event (local or remote wake-up) the PxOut keep their
limp home value.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 August 2010
Table
18).
UJA1023
© NXP B.V. 2010. All rights reserved.
LIN-I/O slave
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