UJA1023T/2R04,512 NXP Semiconductors, UJA1023T/2R04,512 Datasheet - Page 19

• Manufacturer Part Number: UJA1023T/2R04,512
• Description: IC CAN/LIN I/O SLAVE 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1023T/2R04,512

• Applications: LIN Controller
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 6.5 V ~ 27 V
• Package / Case: 16-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281302512; UJA1023T/2R04; UJA1023T/2R04

NXP Semiconductors
UJA1023
Product data sheet
Table 18.
Table 19
transmitter, selection between classic or enhanced checksum model, limp home output
value and PWM initial value. It is selected only if D3.7 = 1 and D3.6 = 0.
Table 19.
[1]
Table 20.
Byte
D4 and D5 7 to 0
D6
D7
Data
byte
D0
D1
D2
D3
D4
D5
D6
D7
Byte
D0
D1
D2
[1]
r = reserved, must be ‘0’.
shows the third configuration data block, that is used to define the slope of the
7
NAD7
0
1
1
LH7
PWM7
1
1
Second I/O configuration data block bit description
Third I/O configuration data block bit allocation
Third I/O configuration data block bit description
Bit
7 to 0
7 to 0
Bit
7 to 0
7 to 0
7 to 0
All information provided in this document is subject to legal disclaimers.
6
NAD6
0
0
0
LH6
PWM6
1
1
Symbol
CM0_[7:0],
CM1_[7:0]
TH2 and TH1 Threshold select. If logic 0 (= TH1), selects V
LWM_[7:0]
SID[7:0]
Symbol
NAD[7:0]
PCI[7:0]
Rev. 5 — 17 August 2010
5
NAD5
0
1
r
LH5
PWM5
1
1
Description
Slave node address (NAD). NAD values are in the range from
1 to 127, while 0 and 128 to 255 are reserved for other
purposes. The slave node address is assigned with the assign
NAD command (see
Protocol control information.
Service identifier. As SlaveResp the RSID value will be 0xF4.
Description
Capture mode for I/O pin Px.
CM1_x
0
0
1
1
threshold. If logic 1 (= TH2) selects V
except in Cyclic sense mode, then V
Local wake-up mask. If LWM_x = 1, the corresponding Px
pin is configured as local wake-up pin. LWM_x is ignored if
Px is configured as switch matrix.
4
NAD4
0
1
r
LH4
PWM4
1
1
3
NAD3
0
0
r
LH3
PWM3
1
1
CM0_x
0
1
0
1
Table
2
NAD2
1
1
r
LH2
PWM2
1
1
5).
no capture
falling edge
rising edge
both edges
…continued
1
NAD1
0
0
LSC
LH1
PWM1
1
1
th3
th2
UJA1023
is selected.
© NXP B.V. 2010. All rights reserved.
as input threshold,
0
NAD0
0
0
ECC
LH0
PWM0
1
1
th1
LIN-I/O slave
as input
Default
value
(hex)
NAD
04
B4
80
00
00
FF
FF
19 of 49