PCA9698DGG/S911,51 NXP Semiconductors, PCA9698DGG/S911,51 Datasheet - Page 19

• Manufacturer Part Number: PCA9698DGG/S911,51
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9698DGG/S911,51

• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Includes: POR
• For Use With: OM6281 - DAUGHTER CARD PCA9698 FOR OM6275
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285491518; PCA9698DGG/S911-T; PCA9698DGG/S911-T

NXP Semiconductors
PCA9698
Product data sheet
7.11 SMBus Alert output (SMBALERT)
The interrupt output pin (INT) can also be used as an Alert line (SMBALERT).
The SMBALERT pins of multiple devices with this feature can be connected together to
form a wired-AND signal and can be used in conjunction with the SMBus Alert Response
Address. ‘SMBus Alert’ message is 2 bytes long and allows the master to determine
which device generated the Alert (SMBALERT going LOW).
When SMBA bit = 1 (register 2Ah, bit 4), the PCA9698 supports the SMBus Alert function
and its INT/SMBALERT pin may be connected as an SMBus Alert signal.
When a master device senses that an ‘SMBus Alert’ condition is present on the ALERT
line (SMBALERT pin of the PCA9698 and/or other devices going LOW):
Remark: If the master initiates an ‘SMBus Alert’ sequence with a Write Command, none
of the slave devices acknowledge. The SMBALERT is open-drain and requires a pull-up
resistor to V
Remark: If the master sends an ACK after reading the I
device keeps sending ‘1’s until a NACK is received.
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It accesses the slave device(s) through the Alert Response Address (ARA)
associated with a Read Command: Start − 0001 100 + R/W = 1.
If the PCA9698 is the device that generated the ‘SMBus Alert’ condition (and its
SMBA bit = 1), it will acknowledge the SMBus Alert command and respond by
transmitting its slave address on the SDA line. The 8
byte will be a zero.
The device will acknowledge an ARA command only if the SMBALERT signal has
been previously asserted (SMBALERT = LOW).
If more than one device pulls its SMBALERT pin LOW, the highest priority (lowest
I
during the slave address transfer.
If the PCA9698 wins the arbitration, its SMBALERT pin will become inactive (will go
HIGH) at the completion of the slave address transmission (9
phase).
If the PCA9698 loses the arbitration, its SMBALERT pin will remain active (will stay
LOW).
The master ends the sequence by sending a NACK and then STOP command.
If the SMBALERT is still LOW after transfer is complete, it means that more than one
device made the request. Another full transaction is then required.
2
C-bus address) device will win communication rights via standard I
DD
.
All information provided in this document is subject to legal disclaimers.
40-bit Fm+ I
Rev. 3 — 3 August 2010
2
C-bus advanced I/O port with RESET, OE and INT
2
th
C-bus slave address, the slave
bit (LSB) of the slave address
th
clock pulse, NACK
PCA9698
© NXP B.V. 2010. All rights reserved.
2
C-bus arbitration
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