A000003 Arduino, A000003 Datasheet - Page 141
![MCU, MPU & DSP Development Tools MINI](/photos/36/49/364973/arduino_mini_sml.jpg)
A000003
Manufacturer Part Number
A000003
Description
MCU, MPU & DSP Development Tools MINI
Manufacturer
Arduino
Series
-r
Type
MCUr
Specifications of A000003
Processor To Be Evaluated
Atmega328
Processor Series
ATmega
Data Bus Width
8 bit
Interface Type
USB, RS-232
Operating Supply Voltage
7 V to 9 V
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega168
- Current page: 141 of 378
- Download datasheet (8Mb)
17.5
2545S–AVR–07/10
Output Compare Unit
Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter
Control Register B (TCCR2B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.
For more details about advanced counting sequences and waveform generation, see
Operation” on page
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by
the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a
match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)
bits. The max and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation
Figure 17-3
count
direction
clear
clk
top
bottom
Tn
T2
shows a block diagram of the Output Compare unit.
DATA BUS
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTn
144.
T2
). clk
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalizes that TCNT2 has reached maximum value.
Signalizes that TCNT2 has reached minimum value (zero).
T2
direction
can be generated from an external or internal clock source,
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
Prescaler
(“Modes of Operation” on page
ATmega48/88/168
T2
in the following.
Oscillator
T/C
clk
I/O
TOSC2
TOSC1
“Modes of
144).
141
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