PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 61

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 6-1:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally
WREN: Write Enable bit
1 = Allows erase or write cycles
0 = Inhibits erase or write cycles
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle completed
RD: Read Control bit
1 = Initiates a memory read
0 = Read completed
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
EEPGD
R/W-x
Note:
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
CFGS
R/W-x
S = Settable only
-n = Value at POR
U-0
—
R/W-0
FREE
WRERR
PIC18F1220/1320
R/W-x
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
WREN
R/W-0
‘0’ = Bit is cleared
R/S-0
WR
DS39605C-page 59
R/S-0
RD
bit 0