PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 36

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
4.1
A Power-on Reset pulse is generated on-chip when
V
circuitry, just tie the MCLR pin through a resistor (1k to
10 k ) to V
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
(parameter D004). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 4-2:
4.2
The Power-up Timer (PWRT) of the PIC18F1220/1320 is
an 11-bit counter, which uses the INTRC source as the
clock input. This yields a count of 2048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in Reset.
The power-up time delay will vary from chip-to-chip due
to V
parameter 33 for details.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
DS39605C-page 34
DD
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR
, temperature and process variation. See DC
V
Power-on Reset (POR)
Power-up Timer (PWRT)
2: R < 40 k is recommended to make sure that
3: R1
DD
DD
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
static
Overstress (EOS).
. This will eliminate external RC compo-
V
DD
1 k
R
C
Discharge
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
PP
will limit any current flowing into
DD
pin breakdown due to Electro-
DD
R1
power-up slope is too slow.
powers down.
(ESD)
DD
PIC18FXXXX
MCLR
POWER-UP)
DD
or
is specified
Electrical
4.3
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most low-power modes.
4.4
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provide a fixed time-out that
is sufficient for the PLL to lock to the main oscillator fre-
quency. This PLL lock time-out (T
and follows the Oscillator Start-up Time-out.
4.5
A configuration bit, BOR, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If V
greater than T
tion will reset the chip. A Reset may not occur if V
falls below V
remain in Brown-out Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once V
will execute the additional time delay. Enabling BOR
Reset does not automatically enable the PWRT.
4.6
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
DD
rises above V
for
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
DD
DD
BOR
an
BOR
falls below V
rises above V
(parameter 35), the brown-out situa-
for less than T
additional
BOR
DD
; it then will keep the chip in
 2004 Microchip Technology Inc.
drops below V
BOR
BOR
time
(parameter D005) for
DD
, the Power-up Timer
PLL
BOR
rises above V
) is typically 2 ms
delay,
. The chip will
BOR
while the
T
PWRT
BOR
DD
.