PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 305

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Timing Diagrams
 2004 Microchip Technology Inc.
A/D Conversion ........................................................ 267
Asynchronous Reception ......................................... 144
Asynchronous Transmission .................................... 141
Asynchronous Transmission
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 145
Brown-out Reset (BOR) ........................................... 262
Capture/Compare/PWM (All CCP Modules) ............ 264
CLKO and I/O .......................................................... 261
Clock/Instruction Cycle .............................................. 45
EUSART Synchronous Receive
EUSART SynchronousTransmission
External Clock (All Modes Except PLL) ................... 259
Fail-Safe Clock Monitor ............................................ 183
Low-Voltage Detect .................................................. 168
Low-Voltage Detect Characteristics ......................... 255
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 147
Slow Rise Time (MCLR Tied to V
Synchronous Reception
Synchronous Transmission ...................................... 148
Synchronous Transmission
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 263
Transition for Entry to SEC_IDLE Mode .................... 24
Transition for Entry to SEC_RUN Mode .................... 26
Transition for Entry to Sleep Mode ............................ 22
(Back to Back) .................................................. 142
Normal Operation ............................................. 145
(Master/Slave) .................................................. 266
(Master/Slave) .................................................. 265
Auto-Restart Disabled) ..................................... 128
Auto-Restart Enabled) ..................................... 128
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 262
V
(Master Mode, SREN) ...................................... 150
(Through TXEN) ............................................... 149
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
Rise > T
PWRT
DD
DD
) ............................................ 40
) ........................................... 40
, V
DD
DD
DD
), Case 1 ....................... 39
), Case 2 ....................... 39
Rise T
DD
,
PWRT
) .............. 39
Timing Diagrams and Specifications ............................... 259
Top-of-Stack Access .......................................................... 42
TSTFSZ ........................................................................... 231
Two-Speed Start-up ..................................................171, 181
Two-Word Instructions ....................................................... 46
TXSTA Register
W
Watchdog Timer (WDT) ............................................171, 180
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 231
XORWF ........................................................................... 232
Transition for Two-Speed Start-up
Transition for Wake from PRI_IDLE Mode ................ 23
Transition for Wake from RC_RUN Mode
Transition for Wake from SEC_RUN Mode
Transition for Wake from Sleep (HSPLL) .................. 22
Transition to PRI_IDLE Mode .................................... 23
Transition to RC_IDLE Mode ..................................... 25
Transition to RC_RUN Mode ..................................... 27
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 261
EUSART Synchronous Receive
EUSART Synchronous Transmission
External Clock Requirements .................................. 259
Internal RC Accuracy ............................................... 260
PLL Clock, HS/HSPLL Mode
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
Example Cases .......................................................... 46
BRGH Bit ................................................................. 135
Associated Registers ............................................... 181
Control Register ....................................................... 180
During Oscillator Failure .......................................... 182
Programming Considerations .................................. 180
(INTOSC to HSPLL) ........................................ 181
(RC_RUN to PRI_RUN) .................................... 25
(HSPLL) ............................................................. 24
(All CCP Modules) ........................................... 265
Requirements .................................................. 266
Requirements .................................................. 265
(V
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 263
Requirements .................................................. 264
PIC18F1220/1320
DD
= 4.2V to 5.5V) ........................................ 260
DS39605C-page 303