PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 213

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
Q1
Q1
PC
CNT
If CNT
If CNT
Q1
No
No
No
PC =
PC =
=
=
=
register ‘f’
operation
operation
operation
Decrement f, skip if 0
[ label ] DECFSZ f [,d [,a]]
0
d
a
(f) – 1
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
Q2
Q2
Q2
No
No
No
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
f
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
11da
GOTO
DECFSZ
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
ffff
CNT
LOOP
destination
operation
operation
operation
Write to
Q4
Q4
Q4
No
No
No
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
Q1
PIC18F1220/1320
No
No
No
PC
PC
register ‘f’
operation
operation
operation
Decrement f, skip if not 0
[ label ] DCFSNZ
0
d
a
(f) – 1
skip if result
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead, making it a two-
cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
Q2
Q2
Q2
No
No
No
f
[0,1]
[0,1]
255
by a 2-word instruction.
=
=
=
=
=
dest,
DCFSNZ TEMP
:
:
11da
operation
operation
operation
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
Process
0
Data
Q3
Q3
Q3
No
No
No
DS39605C-page 211
ffff
f [,d [,a]]
destination
operation
operation
operation
Write to
Q4
Q4
Q4
No
No
No
ffff