PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 164

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
17.5
The selection of the automatic acquisition time and the
A/D conversion clock is determined, in part, by the low-
power mode clock source and frequency while in a
low-power mode.
If the A/D is expected to operate while the device is
in a low-power mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the low-power mode clock that will be
used. After the low-power mode is entered (either of
the Run modes), an A/D acquisition or conversion may
be started. Once an acquisition or conversion is
started, the device should continue to be clocked by the
same low-power mode clock source until the conver-
sion has been completed. If desired, the device may be
placed into the corresponding low-power (ANY)_IDLE
mode during the conversion.
If the low-power mode clock frequency is less than
1 MHz, the A/D RC clock source should be selected.
Operation in the Low-Power Sleep mode requires the
A/D RC clock to be selected. If bits, ACQT2:ACQT0, are
set to ‘000’ and a conversion is started, the conversion
will be delayed one instruction cycle to allow execution
of the SLEEP instruction and entry to Low-Power Sleep
mode. The IDLEN and SCS bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
DS39605C-page 162
Operation in Low-Power Modes
17.6
The ADCON1, TRISA and TRISB registers all configure
the A/D port pins. The port pins needed as analog inputs
must have their corresponding TRIS bits set (input). If
the TRIS bit is cleared (output), the digital output level
(V
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
OH
Note 1: When reading the Port register, all pins
or V
2: Analog levels on any pin defined as a
Configuring Analog Port Pins
OL
) will be converted.
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert an
analog input. Analog levels on a digitally
configured
converted.
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
 2004 Microchip Technology Inc.
input
will
be
accurately