PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 18

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
2.7.1
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating in
power managed modes. The available clock sources are
the primary clock (defined in Configuration Register 1H),
the secondary clock (Timer1 oscillator) and the internal
oscillator block. The clock selection has no effect until a
SLEEP instruction is executed and the device enters a
power managed mode of operation. The SCS bits are
cleared on all forms of Reset.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz), or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the primary clock is providing the system
clock in Primary Clock modes. The IOFS bit indicates
FIGURE 2-8:
DS39605C-page 16
T1OSO
T1OSI
OSC2
OSC1
OSCILLATOR CONTROL REGISTER
Primary Oscillator
Secondary Oscillator
PIC18F1220/1320 CLOCK DIAGRAM
OSCCON<6:4>
Oscillator
Internal
INTRC
Source
Sleep
T1OSCEN
Enable
Oscillator
Block
(INTOSC)
8 MHz
PIC18F1220/1320
500 kHz
250 kHz
125 kHz
31 kHz
4 MHz
2 MHz
1 MHz
8
OSCCON<6:4>
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes or
during
(T1CON<6>) indicates when the Timer1 oscillator is
providing the system clock in Secondary Clock modes.
In power managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the system clock, or the internal
oscillator block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed modes. The uses
of these bits are discussed in more detail in
Section 3.0 “Power Managed Modes”.
111
110
101
100
011
010
001
000
4 x PLL
Note 1: The Timer1 oscillator must be enabled to
2: It is recommended that the Timer1 oscil-
Two-Speed
Clock Source Option
for Other Modules
CONFIG1H <3:0>
HSPLL
LP, XT, HS, RC, EC
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a
executing a SLEEP instruction will be
ignored.
lator be operating and stable before exe-
cuting the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
Internal Oscillator
secondary
T1OSC
Start-ups.
 2004 Microchip Technology Inc.
Control
Clock
clock
The
source
WDT, FSCM
OSCCON<1:0>
Peripherals
IDLEN
T1RUN
CPU
when
bit