PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 26

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
3.3.2
In SEC_IDLE mode, the CPU is disabled, but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the Idle bit,
modifying bits, SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
(see Figure 3-5) to the Timer1 oscillator, the primary
oscillator is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
FIGURE 3-5:
FIGURE 3-6:
DS39605C-page 24
Peripheral
Note:
Program
Counter
T1OSI
OSC1
Clock
Clock
CPU
Note 1: T
CPU Clock
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
SEC_IDLE MODE
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q1
Q2
Wake from Interrupt Event
OST
PC
Q3
= 1024 T
PC
Q4
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q1
OSC
Q1
1
; T
T
OST
PLL
2
(1)
= 2 ms (approx). These intervals are not shown to scale.
Q2
PC + 2
3
OSTS bit Set
Clock Transition
T
Q3
PLL (1)
4
Q4
5
PC + 2
6
Q1
1
2
7
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After a 10 s
delay following the wake event, the CPU begins exe-
cuting code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switchback to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
Clock Transition
3
8
4
5
PC + 4
6
7
8
 2004 Microchip Technology Inc.
Q2
Q3 Q4
Q1
PC + 6
Q2
Q3