PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 304

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
Registers
RESET ............................................................................. 221
Reset .......................................................................... 33, 171
RETFIE ............................................................................ 222
RETLW ............................................................................. 222
RETURN .......................................................................... 223
Return Address Stack ........................................................ 42
Return Stack Pointer (STKPTR) ........................................ 42
Revision History ............................................................... 293
RLCF ................................................................................ 223
RLNCF ............................................................................. 224
RRCF ............................................................................... 224
RRNCF ............................................................................. 225
S
SETF ................................................................................ 225
SLEEP .............................................................................. 226
Sleep
DS39605C-page 302
ADCON0 (A/D Control 0) ......................................... 155
ADCON1 (A/D Control 1) ......................................... 156
ADCON2 (A/D Control 2) ......................................... 157
BAUDCTL (Baud Rate Control) ............................... 134
CCP1CON (Enhanced CCP1 Control) ..................... 115
CONFIG1H (Configuration 1 High) .......................... 172
CONFIG2H (Configuration 2 High) .......................... 174
CONFIG2L (Configuration 2 Low) ............................ 173
CONFIG3H (Configuration 3 High) .......................... 175
CONFIG4L (Configuration 4 Low) ............................ 175
CONFIG5H (Configuration 5 High) .......................... 176
CONFIG5L (Configuration 5 Low) ............................ 176
CONFIG6H (Configuration 6 High) .......................... 177
CONFIG6L (Configuration 6 Low) ............................ 177
CONFIG7H (Configuration 7 High) .......................... 178
CONFIG7L (Configuration 7 Low) ............................ 178
DEVID1 (Device ID 1) .............................................. 179
DEVID2 (Device ID 2) .............................................. 179
ECCPAS (ECCP Auto-Shutdown Control) ............... 127
EECON1 (Data EEPROM Control 1) ................... 59, 68
INTCON (Interrupt Control) ........................................ 75
INTCON2 (Interrupt Control 2) ................................... 76
INTCON3 (Interrupt Control 3) ................................... 77
IPR1 (Peripheral Interrupt Priority 1) .......................... 82
IPR2 (Peripheral Interrupt Priority 2) .......................... 83
LVDCON (LVD Control) ........................................... 167
OSCCON (Oscillator Control) .................................... 17
OSCTUNE (Oscillator Tuning) ................................... 15
PIE1 (Peripheral Interrupt Enable 1) .......................... 80
PIE2 (Peripheral Interrupt Enable 2) .......................... 81
PIR1 (Peripheral Interrupt
PIR2 (Peripheral Interrupt
PWM1CON (PWM Configuration) ............................ 126
RCON (Reset Control) ......................................... 56, 84
RCSTA (Receive Status and Control) ...................... 133
Status ......................................................................... 55
STKPTR (Stack Pointer) ............................................ 43
T0CON (Timer0 Control) ............................................ 99
T1CON (Timer 1 Control) ......................................... 103
T2CON (Timer 2 Control) ......................................... 109
T3CON (Timer3 Control) .......................................... 111
TXSTA (Transmit Status and Control) ..................... 132
WDTCON (Watchdog Timer Control) ....................... 180
and Associated Registers .......................................... 42
OSC1 and OSC2 Pin States ...................................... 18
Request (Flag) 1) ............................................... 78
Request (Flag) 2) ............................................... 79
Software Simulator (MPLAB SIM) .................................... 234
Software Simulator (MPLAB SIM30) ................................ 234
Special Event Trigger. See Compare.
Special Features of the CPU ........................................... 171
Special Function Registers ................................................ 49
Stack Full/Underflow Resets .............................................. 43
SUBFWB ......................................................................... 226
SUBLW ............................................................................ 227
SUBWF ............................................................................ 227
SUBWFB ......................................................................... 228
SWAPF ............................................................................ 228
T
TABLAT Register ............................................................... 60
Table Pointer Operations (table) ........................................ 60
TBLPTR Register ............................................................... 60
TBLRD ............................................................................. 229
TBLWT ............................................................................. 230
Time-out Sequence ........................................................... 34
Timer0 ................................................................................ 99
Timer1 .............................................................................. 103
Timer2 .............................................................................. 109
Timer3 .............................................................................. 111
Configuration Registers ....................................172–178
Map ............................................................................ 49
16-Bit Mode Timer Reads and Writes ...................... 101
Associated Registers ............................................... 101
Clock Source Edge Select (T0SE Bit) ..................... 101
Clock Source Select (T0CS Bit) ............................... 101
Operation ................................................................. 101
Overflow Interrupt .................................................... 101
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ............................. 101
16-Bit Read/Write Mode .......................................... 106
Associated Registers ............................................... 108
Interrupt ................................................................... 106
Operation ................................................................. 104
Oscillator ...........................................................103, 105
Overflow Interrupt .................................................... 103
Resetting, Using a Special Event
Special Event Trigger (CCP) ................................... 117
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
Use as a Real-Time Clock ....................................... 107
Associated Registers ............................................... 110
Operation ................................................................. 109
Output ...................................................................... 110
Postscaler. See Postscaler, Timer2.
PR2 Register ....................................................109, 119
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 109
TMR2 to PR2 Match Interrupt ...................109, 110, 119
Associated Registers ............................................... 113
Operation ................................................................. 112
Oscillator ...........................................................111, 113
Overflow Interrupt .............................................111, 113
Special Event Trigger (CCP) ................................... 113
TMR3H Register ...................................................... 111
TMR3L Register ....................................................... 111
Layout Considerations ..................................... 106
Trigger Output (CCP) ....................................... 106
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