PIC12C671-04I/P Microchip Technology Inc., PIC12C671-04I/P Datasheet - Page 53
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PIC12C671-04I/P
Manufacturer Part Number
PIC12C671-04I/P
Description
8 PIN, 1.75 KB OTP, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12C671-04IP.pdf
(129 pages)
Specifications of PIC12C671-04I/P
A/d Inputs
4-Channel, 8-Bit
Cpu Speed
2.5 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Type
OTP
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
9.0
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC12C67X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
• Oscillator selection
• Reset
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
The PIC12C67X has a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
REGISTER 9-1:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
1999 Microchip Technology Inc.
bit13
bit 13-8, CP<1:0>: Code Protection bit pairs
bit 7:
bit 4:
bit 3:
bit 2-0:
Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
CP1
6-5:
SPECIAL FEATURES OF THE
CPU
CP0
11 = Code protection off
10 = Locations 400h through 7FEh code protected (do not use for PIC12C671 and PIC12CE673)
01 = Locations 200h through 7FEh code protected
00 = All memory is code protected
MCLRE: Master Clear Reset Enable bit
1 = Master Clear Enabled
0 = Master Clear Disabled
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<2:0>: Oscillator Selection bits
111 = EXTRC, Clockout on OSC2
110 = EXTRC, OSC2 is I/O
101 = INTRC, Clockout on OSC2
100 = INTRC, OSC2 is I/O
011 = Invalid Selection
010 = HS Oscillator
001 = XT Oscillator
000 = LP Oscillator
CP1
CP0
CONFIGURATION WORD
CP1
CP0 MCLRE
(1)
CP1
CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The INTRC/EXTRC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
9.1
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h-
3FFFh),
programming.
Configuration Bits
which
can
be
bit0
PIC12C67X
accessed
Register:
Address
DS30561B-page 53
only
CONFIG
2007h
during