PIC12C671-04I/P Microchip Technology Inc., PIC12C671-04I/P Datasheet - Page 48
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PIC12C671-04I/P
Manufacturer Part Number
PIC12C671-04I/P
Description
8 PIN, 1.75 KB OTP, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12C671-04IP.pdf
(129 pages)
Specifications of PIC12C671-04I/P
A/d Inputs
4-Channel, 8-Bit
Cpu Speed
2.5 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Type
OTP
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
PIC12C67X
8.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (R
impedance directly affect the time required to charge
the capacitor C
impedance varies over the device voltage (V
Figure 8-2.
ance for analog sources is 10 k . After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error
is used (512 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
EQUATION 8-1:
V
or
Tc = -(51.2 pF)(1 k
Example 8-1 shows the calculation of the minimum
required acquisition time T
based on the following system assumptions.
Rs = 10 k
1/2 LSb error
V
Temp (system max.) = 50 C
V
FIGURE 8-2:
DS30561B-page 48
HOLD
DD
HOLD
= 5V
= (V
= 0 @ t = 0
A/D Sampling Requirements
REF
Rss = 7 k
The maximum recommended imped-
S
- (V
) and the internal sampling switch (R
REF
HOLD
ANALOG INPUT MODEL
+ R
Legend: C
/512)) • (1 - e
VA
SS
. The sampling switch (R
A/D MINIMUM CHARGING
TIME
+ R
Rs
V
I leakage
R
SS
C
T
PIN
IC
HOLD
S
ACQ
) ln(1/511)
RAx
C
5 pF
HOLD
(-Tc/C
PIN
. This calculation is
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
) must be allowed
HOLD
(R
IC
+ R
V
DD
SS
DD
+ R
), see
V
V
T
T
S
SS
SS
= 0.6V
))
= 0.6V
)
)
)
I leakage
± 500 nA
EXAMPLE 8-1:
T
T
T
T
ACQ
ACQ
ACQ
R
C
IC
Note 1: The reference voltage (V
=
= Internal Amplifier Settling Time +
= 5 s + Tc + [(Temp - 25 C)(0.05 s/ C)]
= 5 s + 5.724 s + [(50 C - 25 C)(0.05 s/ C)]
1k
2: The charge holding capacitor (C
3: The maximum recommended impedance
4: After a conversion has completed, a
Holding Capacitor Charging Time +
Temperature Coefficient
-C
-51.2 pF (1 k + 7 k + 10 k ) ln(0.0020)
-51.2 pF (18 k ) ln(0.0020)
-0.921 s (-6.2146)
5.724 s
10.724 s + 1.25 s
11.974 s
V
SS Rss
DD
HOLD
Sampling
Switch
effect on the equation, since it cancels
itself out.
not discharged after each conversion.
for analog sources is 10 k . This is
required to meet the pin leakage specifi-
cation.
2.0 T
acquisition can begin again. During this
time, the holding capacitor is not con-
nected to the selected A/D input channel.
6V
5V
4V
3V
2V
(R
AD
IC
CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
Sampling Switch
5 6 7 8 9 10 11
delay must complete before
+ R
V
SS
C
= DAC capacitance
= 51.2 pF
( k
SS
HOLD
1999 Microchip Technology Inc.
+ R
)
S
) ln(1/512)
REF
) has no
HOLD
) is