PIC12C671-04I/P Microchip Technology Inc., PIC12C671-04I/P Datasheet - Page 52

• Manufacturer Part Number: PIC12C671-04I/P
• Description: 8 PIN, 1.75 KB OTP, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12C671-04I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 2.5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 5
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12C67X
FIGURE 8-4:
TABLE 8-2:
DS30561B-page 52
Address Name
0Bh/8Bh
0Ch
8Ch
1Eh
1Fh
9Fh
05h
85h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers can be addressed from either bank.
2: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
INTCON
PIR1
PIE1
ADRES
ADCON0
ADCON1
GPIO
TRIS
Selected Channel
Finish Conversion
A/D Clock
ADON = 0?
Wait 2 T
ADIF = 1
ADON = 0
GO = 0?
Device in
SLEEP?
Acquire
= RC?
GO = 0
FLOWCHART OF A/D OPERATION
SUMMARY OF A/D REGISTERS
(1)
No
No
No
No
AD
ADCS1 ADCS0 reserved CHS1
A/D Result Register
SCL
Yes
Yes
Yes
Yes
Bit 7
GIE
—
—
—
—
(2)
Conversion Delayed
1 Instruction Cycle
SDA
Abort Conversion
Power-down A/D
PEIE
ADIF
ADIE
Bit 6
—
—
Start of A/D
ADIF = 0
GO = 0
SLEEP
(2)
TRIS5
Bit 5
T0IE
GP5
—
—
—
TRIS4 TRIS3
INTE
Bit 4
GP4
Finish Conversion
—
—
—
Instruction?
Wait 2 T
ADIF = 1
SLEEP
GO = 0
CHS0
GPIE
Bit 3
GP3
No
AD
—
—
—
Yes
GO/DONE reserved
PCFG2
TRIS2
Bit 2
T0IF
GP2
—
—
Finish Conversion
Power-down A/D
Stay in Sleep
From Sleep?
ADIF = 1
Wake-up
GO = 0
PCFG1
No
TRIS1
Bit 1
INTF
GP1
—
—
Yes
PCFG0 ---- -000
ADON
TRIS0
GPIF
Bit 0
GP0
—
—
1999 Microchip Technology Inc.
Wait 2 T
0000 000x
-0-- ----
-0-- ----
xxxx xxxx
0000 0000
11xx xxxx
--11 1111
AD
Power-on
Value on
Reset
0000 000u
-0-- ----
-0-- ----
uuuu uuuu
0000 0000
---- -000
11uu uuuu
--11 1111
Value on
all other
Resets