PIC12C671-04I/P Microchip Technology Inc., PIC12C671-04I/P Datasheet - Page 23
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PIC12C671-04I/P
Manufacturer Part Number
PIC12C671-04I/P
Description
8 PIN, 1.75 KB OTP, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12C671-04IP.pdf
(129 pages)
Specifications of PIC12C671-04I/P
A/d Inputs
4-Channel, 8-Bit
Cpu Speed
2.5 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Type
OTP
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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4.5
The INDF Register is not a physical register. Address-
ing the INDF Register will cause indirect addressing.
Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS<7>), as shown in Figure 4-4. However, IRP is
not used in the PIC12C67X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
FIGURE 4-4:
1999 Microchip Technology Inc.
RP1 RP0
bank select
For register file map detail see Figure 4-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
Indirect Addressing, INDF and FSR
Registers
(1)
location select
6
Direct Addressing
DIRECT/INDIRECT ADDRESSING
Data
Memory
from opcode
7Fh
00h
Bank 0
00
0
Bank 1
01
Bank 2
10
not used
EXAMPLE 4-1:
NEXT
CONTINUE
Bank 3
11
movlw
movwf
clrf
incf
btfss
goto
:
IRP
bank select
180h
1FFh
(1)
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
INDIRECT ADDRESSING
7
Indirect Addressing
PIC12C67X
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
FSR register
DS30561B-page 23
location select
0
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