VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 97

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

• Test Mode 3: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter
• Test Mode 4: The PHY transmits the sequence of symbols generated by the following scrambler generator
9.12 – MASTER/SLAVE Manual Configuration Enable
When this bit is set to “0” (default), the MASTER/SLAVE designation of the local PHY is determined using the arbitration
protocol established in the IEEE Ethernet standard. When this bit is set to “1”, the MASTER/SLAVE designation of the local PHY
is set by bit 9.11. Note that MASTER/SLAVE configuration is valid only in 1000BASE-T mode.
9.11 – MASTER/SLAVE Configuration Value
This bit is ignored when bit 9.12 is set to “0”. However, if bit 9.12 is set to “1”, bit 9.11 determines the MASTER/SLAVE
designation of the local PHY. If bit 9.12 is set to “1” and bit 9.11 set to “0”, the local PHY is forced to be a SLAVE. If bit 9.12 is set
to “1” and bit 9.11 set to “1”, the local PHY is forced to be a MASTER. Note that MASTER/SLAVE configuration is valid only in
1000BASE-T mode.
9.10 – Port Type
Since the VSC8211 is a single port physical layer transceiver, bit 9.10 is set to “0” by default. When set to “0”, this bit indicates a
preference for operation as a SLAVE. If the Link Partner does not indicate the same preference, the local PHY will operate as a
SLAVE, and the Link Partner will be a MASTER. Otherwise, the normal MASTER/SLAVE assignment protocol is used.
9.9 – 1000BASE-T FDX
Since the VSC8211 is 1000BASE-T FDX capable, this bit is “1” by default. If bit 9.9 is written to be “0”, the Auto-Negotiation
state machine for the local PHY will be blocked from advertising 1000BASE-T FDX. Note that the Link Partner will be notified of
1
VMDS-10105 Revision 4.1
October 2006
The state of this register is internally latched when the Auto-Negotiation state machine enters the ABILITY_DETECT state. Changes to the
states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode.
should use a 125.00 MHz ± 0.01% clock and should operate in SLAVE timing mode.
polynomial, bit generation, and level mappings:
The maximum-length shift register used to generate the sequences defined by this polynomial is updated once
per symbol interval (8ns). The bits stored in the shift register delay line at a particular time n are denoted by
Scrn[10:0]. At each symbol period, the shift register is advanced by one bit, and one new bit represented by
Scrn[0] is generated. Bits Scr
bit sequences, x0
equations, shall be used to generate the quinary symbols, s
should use a 125.00 MHz ± 0.01% clock and should operate in MASTER timing mode.
1
n
, x1
1
n
x2
, and x2
0
0
0
0
1
1
1
1
n
Table 35. Bit Sequences for Generating Quinary Symbols
n
[8] and Scr
x1
n
0
0
1
1
0
0
1
1
, generated from combinations of the scrambler bits as shown in the following
n
1
x0
0
1
0
1
0
1
0
1
n
n
[10] are exclusive-OR'd together to generate the next Scr
1
97 of 165
Quinary Symbol, s
n
, as shown in the following table. The transmitter
-1
-2
-1
0
1
2
0
1
n
n
Datasheet
[0] bit. The
VSC8211