VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet
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VSC8601 10/100/1000BASE-T PHY with RGMII MAC Interface Datasheet VMDS-10210 Revision 4.1 September 2009 ...
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... United States www.vitesse.com Copyright© 2005–2007, 2009 by Vitesse Semiconductor Corporation Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time ...
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Contents Revision History ..........................................................................................9 1 Introduction.....................................................................................13 2 Product Overview.............................................................................14 2.1 Features ........................................................................................................... 14 2.2 Applications....................................................................................................... 15 2.3 Block Diagram ................................................................................................... 16 3 Functional Descriptions....................................................................17 3.1 Interface and Media............................................................................................ 17 3.2 MAC Interface.................................................................................................... 17 3.2.1 MAC Resistor Calibration .......................................................................... 17 3.2.2 ...
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Device Identification ............................................................................... 41 4.2.4 Auto-Negotiation Advertisement ............................................................... 41 4.2.5 Link Partner Auto-Negotiation Capability .................................................... 42 4.2.6 Auto-Negotiation Expansion ..................................................................... 43 4.2.7 Transmit Auto-Negotiation Next Page......................................................... 43 4.2.8 Auto-Negotiation Link Partner Next Page Receive ........................................ 44 4.2.9 1000BASE-T Control................................................................................ ...
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Consumption with 10BASE-T Link.............................................................. 72 5.2.4 Consumption with No Link and ActiPHY Enabled .......................................... 73 5.2.5 Consumption with No Link and ActiPHY Disabled ......................................... 73 5.2.6 Consumption in Power-Down Mode............................................................ 74 5.2.7 Consumption in Reset State ..................................................................... 75 5.3 ...
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Figures Figure 1. Typical Application...................................................................................... 14 Figure 2. High-level Block Diagram ............................................................................ 16 Figure 3. RGMII to Cat5 Block Diagram ...................................................................... 17 Figure 4. RGMII MAC Interface .................................................................................. 18 Figure 5. Cat5 Media Interface .................................................................................. 19 Figure 6. Inline Powered ...
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Tables Table 1. Interface and Media ................................................................................... 17 Table 2. Supported MDI Pair Combinations ................................................................ 21 Table 3. LED Mode and Function Summary ................................................................ 28 Table 4. JTAG Device Identification Register Description .............................................. 35 Table 5. JTAG Interface Instruction Codes ...
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Table 54. DC Characteristics for VDDIOMAC or VDDIOMICRO at 2.5 V............................. 70 Table 55. Current Consumption: 1000BASE-T, Regulator Enabled ................................... 70 Table 56. Current Consumption: 1000BASE-T, Regulator Disabled................................... 71 Table 57. Current Consumption: 100BASE-TX, Regulator Enabled ................................... 71 Table 58. ...
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... Revision 4.0 of this datasheet was published in November 2007. The following is a summary of the changes implemented in the datasheet: • The VSC8601KN package was removed. VSC8601XKN remains available. • The electrostatic discharge voltage values were added. For charged device model ±500. For human body model ±1500. ...
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In the second set, the minimum is 40% and the maximum is 60% and the condition is: register 28E.13:12 set 01. • In the AC characteristics for RGMII compensated, all ...
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The I I values are kept for current consumption with the regulator disabled. VDD12A • For the 100BASE current consumption specifications, all references to the speed were corrected from ...
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In the Identifier 2 register (address 3), which enables device identification, the default for bits 9:4 was modified from TBD to 000010. • In the LED Control register (address 27), the name for bits 2 and 1 was corrected ...
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Introduction This document consists of descriptions and specifications for both functional and physical aspects of the VSC8601 10/100/1000BASE-T PHY with RGMII MAC Interface. In addition to the datasheet, Vitesse maintains an extensive device-specific library of support and collateral materials ...
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Product Overview The VSC8601 device is a low-power Gigabit Ethernet (GbE) transceiver ideal for Gigabit LAN-on-Motherboard applications. The device’s compact, plastic low-profile quad flat package (LQFP) with an exposed pad is optimal for footprint-sensitive applications. Vitesse’s mixed signal and ...
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Legacy Power-over-Ethernet (POE) support. • Powered by a single 3.3 V supply by using the optional on-chip switching regulator. • IEEE 1149.1 JTAG boundary-scan support. • × 10 mm, 64-pin, plastic LQFP package with an exposed pad. ...
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Block Diagram The following illustration shows the primary functional blocks of the VSC8601 device. Figure 2. High-level Block Diagram TX_CLK TXD[3:0] TX_CTL RGMII MAC Jumbo Packet Interface FIFO RX_CLK RXD[3:0] RX_CTL CMODE[3:0] NRESET NSRESET Management MDC and Control MDIO ...
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Functional Descriptions This section provides detailed information about how the VSC8601 device works, what configurations and operational features are available, and how to test its functions. It includes descriptions of the various device interfaces and how to set them ...
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Figure 4. RGMII MAC Interface RGMII MAC ...
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Figure 5. Cat5 Media Interface SimpliPHY TXVP_A_n TXVN_A_n TXVP_B_n TXVN_B_n TXVP_C_n TXVN_C_n TXVP_D_n TXVN_D_n 3.4 Cat5 Auto-Negotiation The VSC8601 device supports twisted pair auto-negotiation as defined by clause 28 of the IEEE standard 802.3-2000. The auto-negotiation process consists of the ...
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For more information about configuring auto-negotiation, see 3.5 Manual MDI/MDI-X Setting As an alternative to automatic MDI/MDI-X detection (using HP Auto-MDIX technology), you can force the PHY to select MDI ...
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The VSC8601 device’s algorithm for HP Auto-MDIX successfully detects, corrects, and operates with any of the MDI wiring pair combinations listed in the following table. Table 2. Supported MDI Pair Combinations RJ-45 Pin Pairings ...
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The VSC8601 device is compatible with switch designs that are intended for use in systems that supply power to Data Terminal Equipment (DTE) using the MDI or twisted pair cable, as described in clause 33 of the IEEE standard 802.3af. ...
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VSC8601 device register bit 26.9, which should and which is subsequently cleared and the interrupt de-asserted after the read device does not loop back the FLP after a specific time, VSC8601 device register ...
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The following illustration shows the relationship between ActiPHY states and timers. Figure 7. ActiPHY State FLP Burst Signal Sent LP Wake-up State 3.10.1 Low-Power State In the low-power state, all major digital blocks are powered down. However, the following functionality ...
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Link Partner Wake-Up State In this state, the PHY attempts to wake up the link partner. FLP bursts are sent on alternating pairs A and B of the Cat5 media for a duration of two seconds. In this state, ...
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Figure 8. SMI Read Frame Station Manager Drives MDIO MDC MDIO Idle Preamble SFD Read PHY Address (optional) Figure 9. SMI Write Frame ...
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MDC to the next rising edge of MDC. When data is being written to the PHY, it must be valid around the rising edge of MDC. Idle The sequence is repeated. 3.11.2 SMI Interrupts The SMI also includes an output ...
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LED Interface The VSC8601 device drives up to three LEDs directly. All LED outputs are active-low and are driven using 3.3 V from the VDD33 power supply. When active, the pins are mainly used to sink current of the ...
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Table 3. LED Mode and Function Summary (continued) Mode Function Name 2 Link100/activity 3 Link10/activity 4 Link100/1000/activity 5 Link10/1000/activity 6 Link10/100/activity 7 Reserved 8 Duplex/collision 9 Collision 10 Activity 11 Reserved 12 Auto-negotiation fault 13 Reserved 14 Force LED off ...
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LED Behavior Several LED behaviors can be programmed into the VSC8601 device. Use the settings in register 17E to program LED behavior, which includes the following: LED Combine Enables an LED to display status for a combination of primary ...
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EPG is enabled necessary to disable the MAC receive pins as well, set register bit 0. When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet packets based on ...
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Figure 12. Far-End Loopback Link Partner Cat5 3.13.4 Near-End Loopback When the near-end loopback testing feature is enabled (by setting the device register bit 0.14 to 1), data on the transmit data pins (TXD) is looped back onto the device ...
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Execute the additional writes in the following order: 1. Enable the 1000BASE-T connector loopback. Set register bit 24 Disable the pair swap correction. Set register bit 18.5 to ...
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IEEE-required signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal NTRST. The following illustration shows the TAP and boundary-scan architecture. Figure 15. Test Access Port and Boundary-Scan Architecture TDI TMS Test Access Port ...
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SAMPLE/PRELOAD Allows a snapshot of inputs and outputs during normal system operation to be taken and examined. It also allows data values to be loaded into the boundary-scan cells prior to the selection of other boundary-scan test instructions. IDCODE Provides ...
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Boundary-Scan Register Cell Order All inputs and outputs are observed in the boundary-scan register cells. All outputs are additionally driven by the contents of boundary-scan register cells. Bidirectional pins have all three related boundary-scan register cells: input, output, and ...
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Configuration The VSC8601 device can be configured using three different methods: • Setting internal memory registers using the management interface. • Setting a combination of CMODE pins and registers. • Loading a configuration into an external EEPROM and connecting ...
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Reserved Registers For main registers 16 through 31 and extended page registers 16E through 30E, any bits marked as “Reserved” should be processed as read only and their states as undefined. 4.1.2 Reserved Bits In writing to registers with ...
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Table 7. Main Registers (continued) Register Address 4.2.1 Mode Control The device register at memory address 0.00.15:0 controls several aspects of VSC8601 functionality. The following table ...
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Table 8. Mode Control, Address 0 (0x00) (continued) Bit Name 11 Power-down 10 Isolate 9 Restart auto-negotiation 8 Duplex 7 Collision test enable 6 MSB for speed selection 5:0 Reserved 4.2.2 Mode Status The register at 1.01.15:0 in the device ...
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Table 9. Mode Status, Address 1 (0x01) (continued) Bit Name 4 Remote fault 3 Auto-negotiation capability 2 Link status 1 Jabber detect 0 Extended capability 4.2.3 Device Identification All 16 bits in both register 2 and register 3 in the ...
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Table 12. Device Auto-Negotiation Advertisement, Address 4 (0x04) Bit Name 12 Reserved technologies 11 Advertise asymmetric pause 10 Advertise symmetric pause 9 Advertise 100BASE-T4 8 Advertise 100BASE-TX FDX 7 Advertise 100BASE-TX HDX 6 Advertise 10BASE-T FDX 5 Advertise 10BASE-T HDX ...
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Auto-Negotiation Expansion The bits in main register 6 work together with those in register 5 to indicate the status of the LP auto-negotiation. The following table lists the available settings and readouts. Table 14. Auto-Negotiation Expansion, Address 6 (0x06) ...
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Auto-Negotiation Link Partner Next Page Receive The bits in register 8 of the main register space work together with register 7 to determine certain aspects of the LP auto-negotiation. The following table lists the possible readouts. Table 16. Auto-Negotiation ...
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Status The bits in register 10 of the main register space allow you to read the status of the 1000BASE-T communications enabled in the device. The following table lists these readouts. Table 18. 1000BASE-T Status, Address 10 (0x0A) ...
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Status Extension Register 16 in the main registers page space of the VSC8601 device provides additional information about the status of the device’s 100BASE-TX operation. Table 20. 100BASE-TX Status Extension, Address 16 (0x10) Bit Name 15 100BASE-TX descrambler ...
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Table 21. 1000BASE-T Status Extension 2, Address 17 (0x11) (continued) Bit Name 9 1000BASE-T SSD error 8 1000BASE-T ESD error 7 1000BASE-T carrier extension error 6 Non-compliant BCM5400 detected 5 MDI crossover error 4:0 Reserved 4.2.15 Bypass Control The bits ...
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Note If bit 1 is set this register, automatic exchange of next pages is disabled, and control is returned to the user through the SMI after the base page is exchanged. The user then must send the ...
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Disconnect Counter The following table lists the readouts you can expect. Table 25. Disconnect Counter, Address 21 (0x15) Bit Name 15:8 Reserved 7:0 Disconnect counter 4.2.19 Extended Control and Status The bits in register 22 provide additional device control ...
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When bits 11:0 are set to 00, the squelch threshold levels are based on the IEEE standard for 10BASE-T. When set to 01, the squelch level is decreased, which may improve the bit error rate performance on long loops. ...
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Table 28. Extended PHY Control 2, Address 24 (0x18) (continued) Bit Name 3:1 Cable length status 0 1000BASE-T connector loopback 4.2.22 Interrupt Mask The bits in register 25 control the device interrupt mask. The following table lists the settings available. ...
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Interrupt Status The status of interrupts already written to the device are available for reading from register 26 in the main registers space. The following table lists the readouts you can expect. Table 30. Interrupt Status, Address 26 (0x1A) ...
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Table 31. LED Control, Address 27 (0x1B) (continued) Bit Name 13 Link 100 LED force on (LED2 pin) 12 Link 100 LED disable (LED2 pin) 11 Link 1000 LED force on (LED1 pin) 10 Link 1000 LED disable (LED1 pin) ...
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Table 32. Auxiliary Control and Status, Address 28 (0x1C) (continued) Bit Name 8 D polarity inversion 7:6 Reserved 5 FDX status 4:3 Speed status 2 Reserved 1 Sticky Reset Enable 0 Reserved 4.2.26 Delay Skew Status The following table lists ...
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Extended Page Registers To provide functionality beyond the IEEE802.3-specified 32 registers and main device registers, the VSC8601 device includes an extended set of registers that provide an additional 15 register spaces. To access the extended page registers (16E through ...
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Extended Page Access The register at address 31 controls the access to the extended page registers for the VSC8601 device. The following table lists the settings available. Table 35. Extended Page Access, Address 31 (0x1F) Bit Name 15:0 Extended ...
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Table 37. Available LED Mode Settings (continued) Mode Bit Setting 11 Reserved 12 1100 13 Reserved 14 1110 15 1111 4.3.3 Enhanced LED Behavior The following table lists the settings available. Table 38. Enhanced LED Behavior, Address 17E (0x11) Bit ...
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Table 38. Enhanced LED Behavior, Address 17E (0x11) (continued) Bit Name 1 LED1 combine feature disable 0 LED0 combine feature disable Note Bit 4 must be set to 1 before register 16E and 17E are enabled for enhanced LED control. ...
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Extended PHY Control 3 Register 20E controls the ActiPHY sleep timer, its wake-up timer, the frequency of the CLKOUT signal, and its link speed downshifting feature. The following table lists the settings available. Table 41. Extended PHY Control 3, ...
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Table 42. EEPROM Interface Status and Control, Address 21E (0x15) Bit Name 14 Re-read EEPROM after software reset 13 Enable EEPROM access 12 EEPROM read or write 11 EEPROM ready 10:0 EEPROM address 4.3.8 EEPROM Data Read/Write Register 22E in ...
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Table 44. Extended PHY Control 4, Address 23E (0x17) (continued) Bit Name 7:0 CRC error counter Note Bits 9:8 are only valid if bit 10 is set. 4.3.10 Reserved Extended Registers The bits in the extended register page space at ...
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Table 45. Extended PHY Control 5, Address 27E (0x1B) (continued) Bit Name 8:6 100BASE-TX transmitter amplitude control 5:3 1000BASE-T transmitter amplitude control 2:0 1000BASE-T edge rate control 4.3.12 RGMII Skew Control The following table lists the settings available. Table 46. ...
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Table 46. RGMII Skew Control, Address 28E (0x1C) (continued) Bit Name 8:0 Reserved 4.3.13 Ethernet Packet Generator (EPG) Control 1 The EPG control register provides access to and control of various aspects of the EPG testing feature. There are two, ...
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Ethernet Packet Generator Control 2 The register at address 30E consists of the second of bits that provide access to and control over various aspects of the EPG testing feature. For information about the first set of EPG control ...
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Functions and Related CMODE Pins The following table lists the pin and bit settings according to the device function and CMODE pin used to configure it. Table 50. Device Functions and Associated CMODE Pins CMODE Function Pin Bit PHY ...
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Table 51. CMODE Resistor Values and Resultant Bit Settings (continued) With CMODE Pin Tied To VSS VSS VSS VSS VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Using resistors with the CMODE pins can be optional in designs that access ...
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VSC8601 device aborts its attempt to connect to the EEPROM and reverts to its otherwise normal operating mode. After the header value is found, the two-byte address value shown in the following table ...
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EEPROM, refer to the EEPROM’s specific datasheet to ensure that write protection on the EEPROM is not set. The following illustration shows the interaction of the VSC8601 device and the EEPROM. Figure ...
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Electrical Specifications This section provides the DC characteristics, AC characteristics, recommended operating conditions, and stress ratings for the VSC8601 device. It includes information on the various timing functions of the device. 5.1 DC Characteristics In addition to any parameter-specific ...
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VDDIO at 2 addition to any parameter-specific conditions, the specifications listed in the following table may be considered valid only when all of these apply: • 2.5 V DDIO • 3.3 V DD33 ...
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Table 55. Current Consumption: 1000BASE-T, Regulator Enabled (continued) Parameter Current with V DDIOMICRO Total power at 3.3 V Total power at 2.5 V The following table shows the current consumption values with a 1000BASE-T link and the on-chip switching regulator ...
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Table 58. Current Consumption: 100BASE-TX, Regulator Disabled (continued) Parameter Current with V DDREG Current with V DD12 Current with V DD12A Current with V DDIOMAC Current with V DDIOMAC Current with V DDIOMICRO Current with V DDIOMICRO Total power at ...
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Consumption with No Link and ActiPHY Enabled The following table shows the current consumption values with no link, ActiPHY enabled, and the on-chip switching regulator enabled. Table 61. Current Consumption: No Link, ActiPHY Enabled, Regulator Enabled Parameter Current with ...
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Table 63. Current Consumption: No Link, ActiPHY Disabled, Regulator Enabled Parameter Current with V DDIOMICRO Total power at 3.3 V Total power at 2.5 V The following table shows the current consumption values with no link, ActiPHY disabled, and the ...
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The following table shows the current consumption values in power-down mode (register address 0. with the regulator disabled. Table 66. Current Consumption: Power-Down, Regulator Disabled Parameter Current with V DD33 Current with V DDREG Current with V DD12 ...
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Reference Clock Input The following table lists the specifications for the reference clock input frequency including various frequencies, duty cycle, and accuracy. Table 68. AC Characteristics for REFCLK Input Parameter Frequency with 25 MHz input Frequency with 125 MHz ...
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JTAG Interface The following table lists the characteristics for the JTAG testing feature. For information about the JTAG interface timing, see Table 71. AC Characteristics for the JTAG Interface Parameter TCK frequency TCK cycle time TCK time high TCK ...
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Table 72. AC Characteristics for the SMI Interface (continued) Parameter Symbol Minimum MDC time high t WH MDC time low t WL Setup to MDC rising t SU Hold from MDC rising t H MDC rise time t R MDC ...
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Table 73. AC Characteristics for Device Reset (continued) Parameter Symbol Soft reset (pin) assertion t SRESET_ASSERT Soft reset (pin) t SRESET_DEASSERT de-assertion Reset rise time t Supply stable time t VDDSTABLE Wait time between soft reset pin de-assert and access ...
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RGMII Uncompensated The following table lists the characteristics when using the device in RGMII uncompensated mode. For more information about the RGMII uncompensated timing, see Figure 21, page 81. Table 74. AC Characteristics for RGMII Uncompensated Parameter Clock frequency ...
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Figure 21. RGMII Uncompensated Timing TX_CLK (at Transmitter) TXD[3:0] TX_CTL TX_CLK (at Receiver) RX_CLK (at Transmitter) RXD[3:0] RX_CTL RX_CLK (at Receiver) 5.3.7 RGMII Compensated The following table lists the characteristics when using the device in RGMII compensated mode. For more ...
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Table 75. AC Characteristics for RGMII Compensated (continued) Parameter Data to clock output hold (at PHY integrated delay) TX_CLK switching threshold Figure 22. RGMII Compensated Timing Delay = 2.0 ns TX_CLK (at Transmitter) TXD[3:0] TX_CTL TX_CLK (at Receiver) Delay = ...
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Table 76. Recommended Operating Conditions (continued) Parameter Power supply voltage for V at 3.3 V Power supply voltage for V 2.5 V Power supply voltage for V 3.3 V Power supply voltage for V Power supply voltage for V Power ...
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Pin Descriptions The VSC8601 device has 64 pins, which are described in this section. The pin information is also provided as an attached Microsoft Excel file, so that you can copy it electronically. In Adobe Reader, double-click the attachment ...
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Pins by Function This section contains the functional pin descriptions for the VSC8601 device. The following table contains notations for definitions of the various pin types. Table 78. Pin Type Symbols Symbol Pin Type I Input I/O Input and ...
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RGMII MAC Interface The following table lists the device pins associated with the RGMII MAC interface. Note that the pins in this table are referenced to VDDIO 3.3 V power supply. Table 80. RGMII MAC Interface Pins Pin Name ...
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Table 80. RGMII MAC Interface Pins (continued) Pin Name 43 OSCEN/CLKOUT 6.2.3 Serial Management Interface (SMI) The following table lists the device pins associated with the device serial management interface (SMI). Note that the pins in this table are referenced ...
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Table 81. SMI Pins (continued) Pin Name 10 EECLK 8 NRESET 6.2.4 JTAG The following table lists the device pins associated with the device JTAG testing facility. Table 82. JTAG Pins Pin Name 3 TDI 2 TDO 5 TMS 6 ...
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Table 83. Miscellaneous Pins (continued) Pin Name 47 PLLMODE 40 LED2 41 LED1 42 LED0 50 REF_REXT 49 REF_FILT 44 REG_EN 46 REG_OUT 48 NC 6.2.6 Power Supply The following table lists the device power supply pins. Table 84. Power ...
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Power Supply and Associated Function Although certain function pins may not be used for a specific application, all power supply pins must be connected to their respective voltage input. Table 85. Power Supply Pins and Associated Function Pins Pins ...
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Pins by Name This section provides an alphabetical list of the VSC8601 pins. CMODE0 CMODE1 CMODE2 CMODE3 EECLK EEDAT LED0 LED1 LED2 MDC MDINT MDIO NC NRESET NSRESET NTRST OSCEN/CLKOUT PLLMODE REF_FILT REF_REXT REG_EN REG_OUT RX_CLK RX_CTL RXD0 RXD1 ...
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Pins by Number This section provides a numeric list of the VSC8601 pins. 1 VDD33 2 TDO 3 TDI 4 VDD12 5 TMS 6 TCK 7 NTRST 8 NRESET 9 EEDAT 10 EECLK 11 VDDIOMICRO 12 MDINT 13 MDC ...
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Package Information The VSC8601 package is a lead(Pb)-free, 64-pin, plastic low-profile quad flat package (LQFP) with an exposed pad × body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1.6 mm maximum height. ...
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Figure 24. Package Drawing Top View Side View - See Detail A Detail Notes 1. All dimensions ...
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... PCB). For more information, see the JEDEC standard. Table 86. Thermal Resistances Part Order Number VSC8601XKN 1. Simulated on the top of the mold compound with the exposed pad soldered to a ground pad on the PCB. 2. Calculated on the exposed pad soldered to a ground pad on the PCB. ...
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Design Considerations This section explains various issues associated with the VSC8601 device. 8.1 RX_CLK Can Reach as High as 55% Duty Cycle Issue: When register 23, bit (no internal clock skew) for RGMII, then the RX_CLK ...
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PhyWrite (PortNo, 31, 0x52B5); // Select internal register page PhyWrite (PortNo, 16, 0xA7F8); // Request read of internal register PhyWriteMsk (PortNo, 17, 0x0018, 0x0018); // Set for forced 100BASE-TX PhyWriteMsk (PortNo, 18, 0, 0); // Necessary read & re-write register ...
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PhyWrite (PortNo, 16, 0x87b4); // Necessary write of internal register PhyWrite (PortNo, 16, 0xa794); // Necessary write of internal register reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var. PhyWrite (PortNo, 18, reg); // Necessary ...
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On-Chip Pull-up Resistor Violation Issue: According to the IEEE standard 802.3, the MDIO pin on a slave device should be an open-drain pad type and drive a low value onto the MDIO shared bus. The MDIO shared bus should ...
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Voltage Overshoot When Using On-Chip Switching Regulator Issue: The device’s on-chip switching regulator generates notable voltage overshoot. Implications: The voltage overshoot from the on-chip switching regulator may lead to device performance issues such as CRC errors, jitter, or both. ...
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High VDD33 and Low VDDIOMAC Supply Issue: If VDD33 is set to the maximum allowed 3.3 V supply and VDDIOMAC is set to the minimum allowed 3.3 V supply, the VSC8601 device can experience performance issues. These issues generally ...
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... IPC and JEDEC standard. The following table lists the ordering information for the VSC8601 device. Table 87. Ordering Information Part Order Number Description VSC8601XKN Revision 4.1 September 2009 Lead(Pb)-free, 64-pin, plastic LQFP with an exposed pad × body size, 1.4 mm body thickness, 0.5 mm pin pitch, and 1 ...