VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 145

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

30 System Timing Specifications
30.1 GMII Mode Transmit Timing (1000BASE-T)
For GMII mode, the following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±10%, and the
MAC/Media Interface Mode Select bits (see
been set to GMII mode.
VMDS-10105 Revision 4.1
October 2006
GTXCLK
TXD[7:0]
T
T
T
T
F
T
GTXCLK-Period
GTXCLK-Setup
GTXCLK-High
GTXCLK-Hold
TOL-GTXCLK
GTXCLK-Low
Symbol
TXEN
TXER
t
t
R
F
-100
Min
2.5
2.5
2.0
0.0
Table 60. GMII Mode Transmit Timing (1000BASE-T) Specifications
Typ
8.0
Figure 37. GMII Transmit AC Timing in 1000BASE-T Mode
T
GTXCLK-High
Max
+100
1.0
1.0
section 25.3.24 “Register 23 (17h) – PHY Control Register #1,”
T
GTX_CLK-Period
Unit
ppm
ns
ns
ns
ns
ns
ns
ns
t
F
145 of 165
0.7V
T
GTXCLK-Low
GTXCLK clock period.
GTXCLK frequency offset tolerance.
GTXCLK minimum pulse width high.
GTXCLK minimum pulse width low.
GMII data TXD[7:0], TXER, TXEN setup time.
GMII data TXD[7:0], TXER, TXEN hold time.
GTXCLK clock rise time, measured from 0.7V to 1.9V.
GTXCLK clock fall time, measured from 0.7V to 1.9V.
T
GTXCLK-Setup
Parameter Description & Conditions
t
R
T
GTXCLK-Hold
page 108) have
Datasheet
VSC8211
1.9V
0.7V
1.9V