SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 67

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

5.4.9
As an option in non-auto mode or transparent mode 0, the internal handling of received
and transmitted CRC checksum can be influenced via control bits CCR3:RCRC and
CCR3:XCRC.
Receive direction:
The received CRC checksum is always assumed to be in the 2 (CRC-CCITT) or 4
(CRC-32) last bytes of a frame, immediately preceding a closing flag. In the version 1 of
ESCC2 a check is performed on the CRC but the received CRC bytes are not transferred
to the RFIFO. In version 2 upwards, if CCR3:RCRC is set, the received CRC checksum
will be written to RFIFO where it precedes the frame status byte (contents of register
RSTA). The received CRC checksum is additionally checked for correctness. If non-auto
mode is selected, the limits for ‘Valid Frame’ check are modified (refer to description of
bit RSTA:VFR).
Transmit direction:
If CCR3:XCRC is set, the CRC checksum is not generated internally. The checksum has
to be provided via the transmit FIFO (XFIFO) as the last two or four bytes. The
transmitted frame will only be closed automatically with a (closing) flag.
Note: The ESCC2 does not check whether the length of the frame, i.e. the number of
5.4.10 Receive Address Handling (version 2 upward)
Mask for Address Detection
The Receive Address Low/High Byte (RAL1/RAH1) can be masked by setting the
corresponding bits in the mask registers (AML/AMH) to allow extended broadcast
address recognition. This feature is applicable to all operating modes with address
recognition (auto mode, non-auto mode and transparent mode 1). It is disabled if all bits
of registers AML and AMH are set to ‘zero’ (RESET value). The function of RAL2/RAH2
and detection of the fixed group address FE
operating mode remain unchanged.
Note: As a very useful option, the detected receive address can be pushed to RFIFO
Receive Address Pushed to RFIFO
As an option in the auto mode, non-auto mode and transparent mode 1, the address field
of received frames can be pushed to RFIFO (first one/two bytes of the frame). This
function is especially useful in conjunction with the extended broadcast address
recognition. It is enabled by setting control bit CCR3:RADD.
Note: In this case the ratio of receive frequency (
Semiconductor Group
bytes, to be transmitted makes sense or not.
(CCR3:RADD).
master clock frequency (
f
f
r
r
/
/
CRC ON/OFF Feature (version 2 upward)
f
f
x
m
1.5 (normal operation),
1.5 (master clock operation).
f
m
) must fulfill:
67
H
or FC
f
r
) to transmit frequency (
H
if applicable to the selected
SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
f
x
) and to
07.96