SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 230

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
Interrupt Status Register 0 (ISR0)
Access: read
Value after RESET: 00
All bits are reset when ISR0 is read. Additionally, TCD and RPF are reset when the
corresponding interrupt vector is output.
Note: If bit IPC:VIS is set to ‘1’, interrupt statuses in ISR0 may be flagged although they
TCD …
PERR …
SCD …
PLLA …
CDSC …
ISR0
are masked via register IMR0. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are they visible in register GIS.
TCD
7
Termination Character Detected
The termination character (TCR) has been received and a data
block is now available in the RFIFO. The actual block length can
be determined by reading register RBCL first.
Parity Error
Only valid if parity check/generation is enabled.
If set, a character with parity error has been received. If enabled
via RFDF, parity error information is stored in RFIFO in the status
byte pertaining to that character.
SYN Character Detected
Only valid in Hunt Mode.
This bit is set if a SYN character is found in the received data
stream after the HUNT command has been issued. The receiver
now is in the synchronous state.
DPLL Asynchronous
This bit is only valid when the receive clock is supplied by the
DPLL and FM0, FM1 or Manchester data encoding is selected.
It is set when the DPLL has lost synchronization. Reception is
disabled (IDLE is inserted) until synchronization has been
regained. Additionally, transmission is also interrupted if the
transmit clock is derived from the DPLL.
Carrier Detect Status Change
Indicates that a state transition has occurred on CD. The actual
state of CD can be read from the VSTR register.
H
0
address: ch-A: 3A
PERR
ch-B: 7A
230
SCD
H
H
PLLA
Detailed Register Description
SAB 82532/SAF 82532
CDSC
RFO
BISYNC Mode
RPF
07.96
0