SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 105

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

9.3
After having performed the initialization, the CPU switches each individual channel of the
ESCC2 into operational phase by setting the PU bit in the CCR0 register.
Initially, the CPU should bring the transmitter and receiver into a defined state by issuing
a Transmitter Reset command (CMDR:XRES) and a Receiver Reset command
(CMDR:RHR in HDLC/SDLC mode, CMDR:RRES in ASYNC and BISYNC mode). If
data reception should be performed, the receiver must be activated by setting the bit
MODE:RAC.
If no ‘Clear To Send’ function is provided via a modem, the CTS pin(s) of the ESCC2
must be connected directly to ground in order to enable data transmission.
Now the ESCC2 is ready to transmit and receive data. Control of data transfer is mainly
done by commands from CPU to ESCC2 via the CMDR register, and by interrupt
indications from ESCC2 to CPU. Additional status information, which does not trigger an
interrupt, is available in the STAR register.
9.3.1
9.3.1.1 Interrupt Mode
In transmit direction 2
channel. After checking the XFIFO status by polling the Transmit FIFO Write Enable bit
(XFW in STAR register) or after a Transmit Pool Ready (XPR) interrupt, up to 32 bytes
may be entered by the CPU into the XFIFO.
HDLC/SDLC: The transmission of a frame can be started by issuing a XTF or XIF
command via the CMDR register. If enabled, a specified number of preambles (refer to
registers CCR3 and PRE) are sent out optionally before transmission of the current
frame starts. If the transmit command does not include an end of message indication
(CMDR: XME), the ESCC2 will repeatedly request for the next data block by means of a
XPR interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte
pool is accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per XME
command, after which frame transmission is finished correctly by appending the CRC
and closing flag sequence. Consecutive frames may share a flag (enabled via
CCR1:SFLG) or may be transmitted as back-to-back frames, if service of XFIFO is quick
enough.
In case no more data is available in the XFIFO prior to the arrival of XME, the
transmission of the frame is terminated with an abort sequence and the CPU is notified
per interrupt (ISR1:XDU). The frame may also be aborted per software (CMDR: XRES).
The data transmission sequence, from the CPU’s point of view, is outlined in figure 46.
Semiconductor Group
Operational Phase
Data Transmission
32 byte FIFO buffers (transmit pools) are provided for each
105
SAB 82532/SAF 82532
Operational Description
07.96