SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 232

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Semiconductor Group
TIN …
CSC …
XMR …
XPR …
Interrupt Mask Register 0, 1 (IMR0, IMR1)
Access: write
Value after RESET: FF
Note: Unused bits have to be set to logical ‘1’.
Each interrupt source can generate an interrupt signal at port INT (function of the output
stage is defined via register IPC). A ‘1’ in a bit position of IMR0 or IMR1 sets the mask
active for the interrupt status in ISR0 or ISR1. Masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are they visible in register GIS.
Moreover, they will
– not be displayed in the Interrupt Status Register if bit IPC:VIS is set to ‘0’
– be displayed in the Interrupt Status Register if bit IPC:VIS is set to ‘1’
Note: After RESET, all interrupts are disabled.
IMR0
IMR1
TCD
7
1
Timer Interrupt
The internal timer has expired (see also description of TIMR
register).
Clear To Send Status Change
Indicates that a state transition has occurred on CTS. The actual
state of CTS can be read from STAR register (CTS bit).
Transmit Message Repeat
The transmission of the last block of characters has to be
repeated because
– a collision occurred while transmitting a character in a bus
– CTS (transmission enable) has been withdrawn during
Transmit Pool Ready
A data block of up to 32 bytes can be written to XFIFO.
H
, FF
configuration, or
transmission of a character in point-to-point configuration.
H
1
1
address: ch-A: 3A
PERR
ALLS
ch-B: 7A
232
SCD
XDU
H
H
(IMR0), 3B
(IMR0), 7B
PLLA
TIN
Detailed Register Description
SAB 82532/SAF 82532
H
H
CDSC
CSC
(IMR1)
(IMR1)
XMR
RFO
BISYNC Mode
RPF
XPR
07.96
0

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