SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 47

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Masked Interrupts Visible in Status Registers (version 2 upward)
The interrupt vector contains only one interrupt at a time: the interrupt displayed in this
vector results from a priority resolution among all unmasked active interrupt statuses.
The Global Interrupt Status register (GIS) points to all interrupt status registers with
active interrupt indications. Register GIS should be evaluated if a pure interrupt polling
scheme is used or if interrupt group 7 or 8 is indicated in the generated interrupt vector.
In version 1 of ESCC2 only unmasked interrupt statuses may:
– generate an interrupt at pin INT,
– generate an interrupt vector,
– be visible in GIS, and
– be visible in the interrupt status registers ISR0_A … B, ISR1_A … B and PIS.
Masked interrupt statuses are only stored internally and they become visible when the
mask is withdrawn.
In version 2 upward, an additional mode can be selected via bit IPC:VIS.
In this mode, masked interrupt status bits still neither generate an interrupt at pin INT nor
generate an interrupt vector nor are visible in GIS, but are displayed in the respective
interrupt status register(s) ISR0_A..B, ISR1_A..B and PIS.
This mode is useful when some interrupt status bits are to generate an interrupt vector
and other status bits are to be polled in the individual interrupt status registers.
Note 1: In the visible mode, all active interrupt status bits, whether the corresponding
Note 2: All unmasked interrupt statuses are treated as before.
Note 3: Please note that whenever polling is used, all interrupt status registers
Semiconductor Group
actual interrupt is masked or not, are reset when the interrupt status register is
read. Thus, when polling of some interrupt status bits is desired, care must be
taken that unmasked interrupts are not lost in the process.
concerned have to be polled individually (no ‘hierarchical’ polling possible),
since GIS only contains information on actually generated – i.e. unmasked
interrupts.
47
Microprocessor Interface
SAB 82532/SAF 82532
07.96