MCP2510-I/SO Microchip Technology, MCP2510-I/SO Datasheet - Page 6

• Manufacturer Part Number: MCP2510-I/SO
• Description: IC CAN CONTRLER IND TEMP 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2510-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP2510
1.3
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4. These blocks and their
functions are described below.
1.4
The heart of the engine is the Finite State Machine
(FSM). This state machine sequences through mes-
sages on a bit by bit basis, changing states as the fields
of the various frame types are transmitted or received.
The FSM is a sequencer controlling the sequential data
stream between the TX/RX Shift Register, the CRC
Register, and the bus line. The FSM also controls the
Error Management Logic (EML) and the parallel data
stream between the TX/RX Shift Registers and the
buffers. The FSM insures that the processes of recep-
tion, arbitration, transmission, and error signaling are
performed according to the CAN protocol. The auto-
matic retransmission of messages on the bus line is
also handled by the FSM.
1.5
The Cyclic Redundancy Check Register generates the
Cyclic Redundancy Check (CRC) code which is trans-
mitted after either the Control Field (for messages with
0 data bytes) or the Data Field, and is used to check the
CRC field of incoming messages.
FIGURE 1-4:
DS21291F-page 6
CAN Protocol Engine
Protocol Finite State Machine
Cyclic Redundancy Check
RX
Sample<2:0>
Decision
CAN PROTOCOL ENGINE BLOCK DIAGRAM
Majority
Receive<7:0>
RecData<7:0>
BusMon
Interface to Standard Buffer
Bit Timing Logic
CRC<14:0>
Comparator
SAM
(Transmit<5:0>, Receive<7:0>)
Transmit<7:0>
TrmData<7:0>
StuffReg<5:0>
Comparator
Shift<14:0>
1.6
The Error Management Logic is responsible for the
fault confinement of the CAN device. Its two counters,
the Receive Error Counter (REC) and the Transmit
Error Counter (TEC), are incremented and decre-
mented by commands from the Bit Stream Processor.
According to the values of the error counters, the CAN
controller is set into the states error-active, error-pas-
sive or bus-off.
1.7
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive to
dominant bus transition at Start of Frame (hard syn-
chronization) and on any further recessive to dominant
bus line transition if the CAN controller itself does not
transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to com-
pensate for the propagation delay time, phase shifts,
and to define the position of the Sample Point within the
bit time. The programming of the BTL depends upon
the baud rate and external physical delay times.
Error Management Logic
Bit Timing Logic
Transmit Logic
Error Counter
Error Counter
Rec/Trm Addr.
Transmit
Protocol
Receive
FSM
© 2007 Microchip Technology Inc.
TX
REC
TEC
ErrPas
BusOff