MCP2510-I/SO Microchip Technology, MCP2510-I/SO Datasheet - Page 35

• Manufacturer Part Number: MCP2510-I/SO
• Description: IC CAN CONTRLER IND TEMP 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2510-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non Return to
Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and syn-
chronized to the transmitters clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times, to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the MCP2510 is implemented using a
DPLL that is configured to synchronize to the incoming
data, and provide the nominal timing for the transmitted
data. The DPLL breaks each bit time into multiple seg-
ments made up of minimal periods of time called the
time quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation, and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the baud
rate prescaler and number of time quanta in each seg-
ment.
FIGURE 5-1:
© 2007 Microchip Technology Inc.
Input Signal
BIT TIMING
T
Q
Q
).
Sync
BIT TIME PARTITIONING
Segment
Prop
Segment 1
Phase
Sample Point
The nominal bit rate is the number of bits transmitted
per second assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
Nominal Bit Time is defined as:
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 5-1.
Nominal Bit Time = T
Phase_Seg1 + Phase_Seg2)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
T
is programmable from a minimum of 8 T
mum of 25 T
bit time is 1 µs, corresponding to a maximum 1 Mb/s
rate.
Q
- Synchronization Segment (Sync_Seg)
- Propagation Time Segment (Prop_Seg)
- Phase Buffer Segment 1 (Phase_Seg1)
- Phase Buffer Segment 2 [Phase_Seg2)
(see Figure 5-1). By definition, the nominal bit time
T
BIT
= 1 / NOMlNAL BlT RATE
Q
. Also, by definition the minimum nominal
Q
Segment 2
* (Sync_Seg + Prop_Seg +
Phase
MCP2510
DS21291F-page 35
Q
to a maxi-