MCP2510-I/SO Microchip Technology, MCP2510-I/SO Datasheet - Page 41

• Manufacturer Part Number: MCP2510-I/SO
• Description: IC CAN CONTRLER IND TEMP 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2510-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
The CAN protocol provides sophisticated error detec-
tion mechanisms. The following errors can be detected.
6.1
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit sequence
from the start of a frame until the end of the data field.
This CRC sequence is transmitted in the CRC Field.
The receiving node also calculates the CRC sequence
using the same formula and performs a comparison to
the received sequence. If a mismatch is detected, a
CRC error has occurred and an error frame is gener-
ated. The message is repeated.
6.2
In the acknowledge field of a message, the transmitter
checks if the acknowledge slot (which has sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An acknowl-
edge error has occurred; an error frame is generated;
and the message will have to be repeated.
6.3
lf a node detects a dominant bit in one of the four seg-
ments including end of frame, interframe space,
acknowledge delimiter or CRC delimiter; then a form
error has occurred and an error frame is generated.
The message is repeated.
6.4
A Bit Error occurs if a transmitter sends a dominant bit
and detects a recessive bit or if it sends a recessive bit
and detects a dominant bit when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the acknowledge slot, no bit error is generated
because normal arbitration is occurring.
6.5
lf, between the start of frame and the CRC delimiter, six
consecutive bits with the same polarity are detected,
the bit stuffing rule has been violated. A stuff error
occurs and an error frame is generated. The message
is repeated.
© 2007 Microchip Technology Inc.
ERROR DETECTION
CRC Error
Acknowledge Error
Form Error
Bit Error
Stuff Error
6.6
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous mes-
sage is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
three error states “error-active”, “error-passive” or “bus-
off” according to the value of the internal error counters.
The error-active state is the usual state where the bus
node can transmit messages and active error frames
(made of dominant bits) without any restrictions. In the
error-passive state, messages and passive error
frames (made of recessive bits) may be transmitted.
The bus-off state makes it temporarily impossible for
the station to participate in the bus communication.
During this state, messages can neither be received
nor transmitted.
6.7
The MCP2510 contains two error counters: the
Receive Error Counter (REC) (see Register 6-2), and
the Transmit Error Counter (TEC) (see Register 6-1).
The values of both counters can be read by the MCU.
These counters are incremented or decremented in
accordance with the CAN bus specification.
The MCP2510 is error-active if both error counters are
below the error-passive limit of 128. It is error-passive
if at least one of the error counters equals or exceeds
128. It goes to bus-off if the transmit error counter
equals or exceeds the bus-off limit of 256. The device
remains in this state, until the bus-off recovery
sequence is received. The bus-off recovery sequence
consists of 128 occurrences of 11 consecutive reces-
sive bits (see Figure 6-1). Note that the MCP2510, after
going bus-off, will recover back to error-active, without
any intervention by the MCU, if the bus remains idle for
128 X 11 bit times. If this is not desired, the error inter-
rupt service routine should address this. The current
error mode of the MCP2510 can be read by the MCU
via the EFLG register (Register 6-3).
Additionally, there is an error state warning flag bit,
EFLG:EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
Error States
Error Modes and Error Counters
MCP2510
DS21291F-page 41